Base Compiler Invocation
C benchmarks
-
- icx
![[user]](https://www.spec.org/auto/accel2023/images/user.png)
- CC, LD
-
The Intel oneAPI C compiler.
Fortran benchmarks
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- ifx
- FC, LD
-
The Intel oneAPI Fortran compiler.
The Intel oneAPI C compiler.
The Intel oneAPI Fortran compiler.
The Intel oneAPI C compiler.
The Intel oneAPI Fortran compiler.
FPORTABILITY flag
use a specific memory model to generate code and store data
small - Restricts code and data to the first 2GB of address space (DEFAULT)
medium - Restricts code to the first 2GB; it places no memory restriction on data
large - Places no memory restriction on code or data
Pass the comma separated arguments to the linker
No Fortran main method exists, use C equivalent instead.
FPORTABILITY flag
use a specific memory model to generate code and store data
small - Restricts code and data to the first 2GB of address space (DEFAULT)
medium - Restricts code to the first 2GB; it places no memory restriction on data
large - Places no memory restriction on code or data
Pass the comma separated arguments to the linker
No Fortran main method exists, use C equivalent instead.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Enable LTO (Link Time Optimization) in 'full' mode.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Enables the loop optimizer and auto-vectorization for OpenMP offloading device compilation when option O2 or higher is set or specified.
Assume that a scalar declare target variable with implicit data-mapping referenced in a 'target' construct has the same value in the host and device environment
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Enable LTO (Link Time Optimization) in 'full' mode.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Enables the loop optimizer and auto-vectorization for OpenMP offloading device compilation when option O2 or higher is set or specified.
Assume that a scalar declare target variable with implicit data-mapping referenced in a 'target' construct has the same value in the host and device environment
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Enable LTO (Link Time Optimization) in 'full' mode.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Enables the loop optimizer and auto-vectorization for OpenMP offloading device compilation when option O2 or higher is set or specified.
Assume that a scalar declare target variable with implicit data-mapping referenced in a 'target' construct has the same value in the host and device environment
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Enable LTO (Link Time Optimization) in 'full' mode.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Enables the loop optimizer and auto-vectorization for OpenMP offloading device compilation when option O2 or higher is set or specified.
Assume that a scalar declare target variable with implicit data-mapping referenced in a 'target' construct has the same value in the host and device environment
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Enable LTO (Link Time Optimization) in 'full' mode.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Assume that a scalar declare target variable with implicit data-mapping referenced in a 'target' construct has the same value in the host and device environment
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Enable LTO (Link Time Optimization) in 'full' mode.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Enables the loop optimizer and auto-vectorization for OpenMP offloading device compilation when option O2 or higher is set or specified.
Assume that a scalar declare target variable with implicit data-mapping referenced in a 'target' construct has the same value in the host and device environment
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Enable LTO (Link Time Optimization) in 'full' mode.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Enables the loop optimizer and auto-vectorization for OpenMP offloading device compilation when option O2 or higher is set or specified.
Assume that a scalar declare target variable with implicit data-mapping referenced in a 'target' construct has the same value in the host and device environment
Flag description origin markings:
|
Indicates that the flag description came from the user flags file. |
![[suite]](https://www.spec.org/auto/accel2023/images/suite.png) |
Indicates that the flag description came from the suite-wide flags file. |
![[benchmark]](https://www.spec.org/auto/accel2023/images/benchmark.png) |
Indicates that the flag description came from a per-benchmark flags file. |
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2023-2025 Standard Performance Evaluation Corporation
Tested with SPEC accel2023 v2.0.18.
Report generated on 2025-01-15 13:17:16 by SPEC accel2023 flags formatter v112 .