SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer p5 575 (1900 MHz, 1 CPU)
SPECint2000 = 1456     
SPECint_base2000 = 1385     
SPEC license # 11 Tested by: IBM Test date: Jan-2005 Hardware Avail: Feb-2005 Software Avail: Dec-2004
Benchmark Reference
Runtime Ratio Graph Scale
164.gzip 1400 160    875     156    899     164.gzip base result bar (875)
164.gzip peak result bar (899)
175.vpr 1400 114    1229      114    1230      175.vpr base result bar (1229)
175.vpr peak result bar (1230)
176.gcc 1100 69.6  1581      69.6  1581      176.gcc base result bar (1581)
176.gcc peak result bar (1581)
181.mcf 1800 76.7  2347      69.8  2580      181.mcf base result bar (2347)
181.mcf peak result bar (2580)
186.crafty 1000 85.7  1167      67.5  1482      186.crafty base result bar (1167)
186.crafty peak result bar (1482)
197.parser 1800 144    1250      144    1250      197.parser base result bar (1250)
197.parser peak result bar (1250)
252.eon 1300 81.2  1601      78.6  1655      252.eon base result bar (1601)
252.eon peak result bar (1655)
253.perlbmk 1800 185    973     169    1064      253.perlbmk base result bar (973)
253.perlbmk peak result bar (1064)
254.gap 1100 89.1  1234      89.1  1234      254.gap base result bar (1234)
254.gap peak result bar (1234)
255.vortex 1900 88.3  2152      82.9  2291      255.vortex base result bar (2152)
255.vortex peak result bar (2291)
256.bzip2 1500 113    1323      111    1351      256.bzip2 base result bar (1323)
256.bzip2 peak result bar (1351)
300.twolf 3000 192    1560      186    1615      300.twolf base result bar (1560)
300.twolf peak result bar (1615)
SPECint_base2000 1385       
  SPECint2000 1456       

Hardware Vendor: IBM Corporation
Model Name: IBM eServer p5 575 (1900 MHz, 1 CPU)
CPU MHz: 1900
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 1 core/chip (SMT off)
CPU(s) orderable: 8
Parallel: no
Primary Cache: 64KBI+32KBD (on chip)
Secondary Cache: 1920KB unified (on chip)
L3 Cache: 36MB unified (off-chip)/DCM, 8 DCM/SUT
Other Cache: None
Memory: 32 GB
Disk Subsystem: 2x36GB SCSI, 15K RPM
Other Hardware: None
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 7.0 for AIX
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information
 Portability Flags:
   176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
   186.crafty:   -DAIX
   252.eon:      srcalt=fmax_errno
   253.perlbmk:  -DSPEC_CPU2000_AIX
   300.twolf:    -DHAVE_SIGNED_CHAR

 Base Optimization Flags:
   C:    -qpdf1/pdf2
         -O5 -blpdata -D_ILS_MACROS
   C++:  -qpdf1/pdf2
         -O5 -lhmu -qalign=natural

 Peak Optimization Flags
   164.gzip:     -qpdf1/pdf2
                 fdpr -q -O3
                 -O5 -blpdata -qfdpr
   175.vpr:      -qpdf1/pdf2
                 -O5 -blpdata -qalign=natural -D_ILS_MACROS
   176.gcc:      -qpdf1/pdf2
                 -O5 -blpdata -D_ILS_MACROS
   181.mcf:      fdpr -q -O3
                 -O5 -blpdata -qfdpr
   186.crafty:   -qpdf1/pdf2
                 fdpr -q -O3
                 -O4 -q64 -qfdpr -qarch=pwr3 -qtune=pwr3
   197.parser:   -qpdf1/pdf2
                 -O5 -blpdata -qalign=natural -D_ILS_MACROS
   252.eon:      -qpdf1/pdf2
                 -O4 -qarch=auto -qtune=auto -qalign=natural -D_ILS_MACROS
   253.perlbmk:  -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural -blpdata -D_ILS_MACROS
   254.gap:      -qpdf1/pdf2
                  -O5 -blpdata -qalign=natural -D_ILS_MACROS
   255.vortex:   -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural -blpdata -D_ILS_MACROS
   256.bzip2:    fdpr -q -O3
                 -O5 -blpdata -qfdpr -D_ILS_MACROS
   300.twolf:    fdpr -q -O3
                 -O5 -blpdata -qfdpr -qalign=natural

 Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
 was used with 252.eon for POSIX-compatibility.

 APAR IY62267 was applied to AIX 5L V5.3 to achieve Mantainence Level 1.

 SMT:  Acronym for "Simultaneous Multi-Threading". A processor technology that allows
       the simultaneous execution of multiple thread contexts within a single processor
       core. (Enabled by default)
 DCM:  Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
       For the 575, only one core is active per chip.
 SUT:  Acronym for "System Under Test"

 ulimits set to unlimited.
 Large page mode and memory affinity were set as follows:
     vmo -r -o lgpg_regions=1664 -o lgpg_size=16777216 -o memory_affinity=1
     chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
     reboot -q
 One core was deconfigured and SMT disabled at the open-firmware prompt, using the
     boot -s cpu=1 -s smt_off

For questions about this result, please contact the tester.
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Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 22-Feb-2005

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