Increase the probability that the compiler will perform memcpy/memset transformations.

Ignore parallelization factors in loop interchange heuristics.

When considering whether to interchange loops, set memory store operation weight to n. A higher value of n indicates a greater performance cost for stores.

Control the optimizer's loop inliner; set the minimum call site frequency counter in order to consider a routine for inlining.

Control the optimizer's loop inliner; Set inline callee size limit to n. The unit roughly corresponds to the number of instructions.

Control the optimizer's loop inliner; The inliner is allowed to increase the size of the program by up to n%.

Control the optimizer's loop inliner; Allow routines to increase by up to n. The unit roughly corresponds to the number of instructions.

Control the optimizer's loop inliner; Perform maximum inlining (without considering code size increase).

Control the optimizer's loop inliner; Allow routines that are called recursively to still be eligible for inlining.

Inliner only considers routines smaller than n pseudo instructions as possible inline candidates.

Increase the probability that loop induction variables will replaced, so that some extraneous code can be eliminated from loops.

Ignore parallelization factors in loop distribution heuristics.

Reconstruct array subscripts during memory allocation merging and data layout program transformation.

Do speculative prefetching for link-list data structures; perform prefetching n iterations ahead.

Do speculative prefetching for link-list data structures; do not attempt prefetching for innermost loops.

Do prefetching for one-level indirect memory references.

Convert multiple short memory operations into single long memory operations.

Perform loop tiling which is enabled by loop skewing. Loop skewing is a transformation that transforms a non-fully interchangeable loop nest to a fully interchangeable loop nest. The optional b<n> sets the tiling block size to n.

Increase the probability that small-trip-count inner loops will be fully unrolled.

Enable optimization of critical control paths

• -fsimple=0 permits no simplifying assumptions. Preserves strict IEEE 754 conformance.
• -fsimple=1 allows the optimizer to assume:
  • The IEEE 754 default rounding/trapping modes do not change after process initialization.
  • Computations producing no visible result other than potential floating-point exceptions may be deleted.
  • Computations with Infinity or NaNs as operands need not propagate NaNs to their results. For example, x*0 may be replaced by 0.
  • Computations do not depend on sign of zero.
• -fsimple=2 permits more aggressive floating point optimizations that may cause programs to produce different numeric results due to changes in rounding. Even with -fsimple=2, the optimizer still is not permitted to introduce a floating point exception in a program that otherwise produces none.

There are several scheduling passes in the compiler. This option allows early passes to move instructions across call instructions.

Allow the enhanced pipeline scheduler (EPS) to use speculative (non-faulting) loads.

Use enhanced pipeline scheduling (EPS) and selective scheduling algorithms for instruction scheduling.

The number of live variables allowed at any given point is n more than the number of physical registers. Setting n to a significantly large number (e.g., 100) will disable register pressure heuristics in EPS.

Set the EPS window size, that is, the number of instructions it will consider across all paths when trying to find independent instructions to schedule a parallel group. Larger values may result in better run time, at the cost of increased compile time.

Sets the aggressiveness of the trace formation, where n is 4, 5, or 6. The higher the value of n, the lower the branch probability needed to include a basic block in a trace.

Turn on optimization to reduce branch after branch penalty: nops will be inserted to prevent one branch from occupying the delay slot of another branch.

Use profile feedback data to predict values and attempt to generate faster code along these control paths, even at the expense of possibly slower code along paths leading to different values. Correct code is generated for all paths.

Do function entry alignment at n-byte boundaries.

Peels the most frequent test branches/cases off a switch until the branch probability reaches less than 1/n. This is effective only when profile feedback is used

Control irregular loop prefetching; turns the module on (1) or off (0) (default is on for F90; off for C/C++)

Control irregular loop prefetching; sets the prefetch look ahead distance, in bytes. The default is 256.

Control irregular loop prefetching; a setting of "1" means force user settings to override internally computed values.

Control irregular loop prefetching; a setting of "1" means force the optimization to be turned on for all languages.

Turns on prefetching for outer loops

Control irregular loop prefetching; use weak prefetches in the general loop prefetch.

Control irregular loop prefetching; sets the number of attempts at prefetching. If not specified, t=2 if -xprefetch_level=3 has been set; otherwise, defaults to t=1.

Specifies that all loops can be pipelined without needing to be concerned about loop-carried dependencies.

In pipelined loops, use floating point divide instructions for signed integer division.

Set number of outstanding prefetches in pipelined loops to <n>

Turn off prefetching in the prolog of modulo scheduled loops.

Turn off prefetching for stores in the pipeliner.

Turn off the use of strong prefetches in modulo scheduled loops.

Assert (to the pipeliner) that unsigned int computations will not overflow.

Reduce the probability that the compiler will hoist sethi insructions out of loops.

• basic assume that memory references that involve different C basic types do not alias each other.
• std assume aliasing rules described in the ISO 1999 C standard.
• strong in addition to the restrictions at the std level, assume that pointers of type char * are used only to access an object of type char; and assume that there are no interior pointers.

• any assumes that any type can alias any other
• simple assumes that fundamental types are not aliased
• compatible assumes that layout-incompatible types are not aliased.

• v8plusb Use instructions that are available on the UltraSPARC-III/IV processors
• native Use the instructions available on the current processor
• generic Use instructions that are compatible with most SPARC processors

• ultra3 Optimize for the UltraSPARC-III processor
• native Optimize for the current processor
• generic Use timing properties for good performance on most SPARC processors

• 0 = off
• 1 = on
• 2 = performs whole-program detection and analysis.

At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.

• -xO1 does only basic local optimizations (peephole.)
• -xO2 Do basic local and global optimizations, such as induction variable elimination, common subexpression elimination, constant propogation, register allocation, and basic block merging.
• -xO3 Add global optimizations at the function level, loop unrolling, and software pipelining.
• -xO4 Adds automatic inlining of functions in the same file.
• -xO5 Uses optmization algorithms that may take significantly more compilation time or that do not have as high a probability of improving execution time, such as speculative code motion.