SPEC(R) CINT2006 Summary Intel Corporation Intel DG965WH motherboard (2.93 GHz, Intel Core 2 Extreme processor X6800) Fri Sep 1 14:18:41 2006 CPU2006 License: 13 Test date: Aug-2006 Test sponsor: Intel Corporation Hardware availability: Jul-2006 Tested by: Intel Corporation Software availability: Aug-2006 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 2 466 41.9 S 400.perlbench 2 466 41.9 * 400.perlbench 2 463 42.2 S 401.bzip2 2 723 26.7 S 401.bzip2 2 702 27.5 * 401.bzip2 2 702 27.5 S 403.gcc 2 867 18.6 S 403.gcc 2 867 18.6 * 403.gcc 2 884 18.2 S 429.mcf 2 511 35.7 S 429.mcf 2 510 35.7 * 429.mcf 2 510 35.8 S 445.gobmk 2 560 37.5 S 445.gobmk 2 556 37.7 * 445.gobmk 2 556 37.8 S 456.hmmer 2 764 24.4 S 456.hmmer 2 760 24.5 S 456.hmmer 2 760 24.5 * 458.sjeng 2 682 35.5 * 458.sjeng 2 683 35.4 S 458.sjeng 2 682 35.5 S 462.libquantum 2 1768 23.4 * 462.libquantum 2 1768 23.4 S 462.libquantum 2 1768 23.4 S 464.h264ref 2 737 60.0 S 464.h264ref 2 736 60.2 * 464.h264ref 2 736 60.2 S 471.omnetpp 2 526 23.8 S 471.omnetpp 2 526 23.8 * 471.omnetpp 2 527 23.7 S 473.astar 2 563 25.0 S 473.astar 2 564 24.9 S 473.astar 2 564 24.9 * 483.xalancbmk 2 350 39.4 S 483.xalancbmk 2 351 39.3 S 483.xalancbmk 2 351 39.4 * ============================================================================== 400.perlbench 2 466 41.9 * 401.bzip2 2 702 27.5 * 403.gcc 2 867 18.6 * 429.mcf 2 510 35.7 * 445.gobmk 2 556 37.7 * 456.hmmer 2 760 24.5 * 458.sjeng 2 682 35.5 * 462.libquantum 2 1768 23.4 * 464.h264ref 2 736 60.2 * 471.omnetpp 2 526 23.8 * 473.astar 2 564 24.9 * 483.xalancbmk 2 351 39.4 * SPECint(R)_rate_base2006 31.1 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Core 2 Extreme X6800 CPU Characteristics: 2.93 GHz, 1066 MHz bus CPU MHz: 2933 FPU: Integrated CPU(s) enabled: 2 cores, 1 chip, 2 cores/chip CPU(s) orderable: 1 chip Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 4 MB I+D on chip per chip L3 Cache: None Other Cache: None Memory: 2 GB (2 1GB Corsair TWIN2X2048-8500C5 DDR2 1066 CL5-5-5) Disk Subsystem: Maxtor DiamondMax 10 6B300S0 300GB NCQ Serial ATA (7200 RPM, 16MB cache) Other Hardware: None SOFTWARE -------- Operating System: Windows XP Professional SP2 32-bit Compiler: Intel C++ Compiler 9.1 for IA32 Build 20060816Z Microsoft Visual Studio .Net 2003 (for libraries) SmartHeap Library Version 8.0 from http://www.microquill.com/ Auto Parallel: No File System: NTFS System State: Default Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: None General Notes ------------- Memory timings set manually to DDR2-800 5-5-5-15 in the bios Base Compiler Invocation ------------------------ C benchmarks: icl -Qvc7.1 -Qc99 C++ benchmarks: icl -Qvc7.1 Base Portability Flags ---------------------- 403.gcc: -DSPEC_CPU_WIN32 464.h264ref: -DSPEC_CPU_NO_INTTYPES -DWIN32 Base Optimization Flags ----------------------- C benchmarks: -fast /F512000000 shlw32m.lib -link /FORCE:MULTIPLE C++ benchmarks: -fast -Qcxx_features /F512000000 shlw32m.lib -link /FORCE:MULTIPLE Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags file that was used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.03.html You can also download the XML flags source by saving the following link: http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.03.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2014 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.0. Report generated on Tue Jul 22 09:55:51 2014 by CPU2006 ASCII formatter v6932. Originally published on 19 September 2006.