SPEC(R) CINT2006 Summary IBM Corporation IBM System x3800 Tue Jan 2 11:19:13 2007 CPU2006 License: 11 Test date: Jan-2007 Test sponsor: IBM Corporation Hardware availability: Oct-2006 Tested by: IBM Corporation Software availability: Aug-2006 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 16 2244 69.7 S 400.perlbench 16 2245 69.6 * 400.perlbench 16 2246 69.6 S 401.bzip2 16 3427 45.1 S 401.bzip2 16 3430 45.0 S 401.bzip2 16 3428 45.0 * 403.gcc 16 6629 19.4 * 403.gcc 16 6630 19.4 S 403.gcc 16 6627 19.4 S 429.mcf 16 3342 43.7 S 429.mcf 16 3343 43.7 S 429.mcf 16 3342 43.7 * 445.gobmk 16 2642 63.5 * 445.gobmk 16 2643 63.5 S 445.gobmk 16 2641 63.5 S 456.hmmer 16 3135 47.6 * 456.hmmer 16 3133 47.6 S 456.hmmer 16 3174 47.0 S 458.sjeng 16 3919 49.4 * 458.sjeng 16 3997 48.4 S 458.sjeng 16 3861 50.1 S 462.libquantum 16 13567 24.4 S 462.libquantum 16 13571 24.4 S 462.libquantum 16 13571 24.4 * 464.h264ref 16 3012 118 S 464.h264ref 16 3004 118 S 464.h264ref 16 3004 118 * 471.omnetpp 16 3690 27.1 S 471.omnetpp 16 3690 27.1 * 471.omnetpp 16 3697 27.1 S 473.astar 16 2383 47.1 S 473.astar 16 2386 47.1 * 473.astar 16 2392 47.0 S 483.xalancbmk 16 1793 61.6 S 483.xalancbmk 16 1798 61.4 * 483.xalancbmk 16 1800 61.3 S ============================================================================== 400.perlbench 16 2245 69.6 * 401.bzip2 16 3428 45.0 * 403.gcc 16 6629 19.4 * 429.mcf 16 3342 43.7 * 445.gobmk 16 2642 63.5 * 456.hmmer 16 3135 47.6 * 458.sjeng 16 3919 49.4 * 462.libquantum 16 13571 24.4 * 464.h264ref 16 3004 118 * 471.omnetpp 16 3690 27.1 * 473.astar 16 2386 47.1 * 483.xalancbmk 16 1798 61.4 * SPECint(R)_rate_base2006 46.0 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon 7110N CPU Characteristics: 667 MHz bus CPU MHz: 2500 FPU: Integrated CPU(s) enabled: 8 cores, 4 chips, 2 cores/chip, 2 threads/core CPU(s) orderable: 1,2,4 chips Primary Cache: 12 K micro-ops I + 16 KB D on chip per core Secondary Cache: 1 MB I+D on chip per core L3 Cache: 4 MB I+D on chip per chip Other Cache: None Memory: 32 GB (16 x 2048 MB ECC PC2-3200) Disk Subsystem: 73 GB SAS, 10k RPM Other Hardware: None SOFTWARE -------- Operating System: Microsoft Windows Server 2003 Enterprise x64 Edition + SP1 (64-bit) Compiler: Intel C++ Compiler for IA32 version 9.1 Build no 20060816 Microsoft Visual Studio .Net 2003 (for libraries) Auto Parallel: No File System: NTFS System State: Default Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: Smart Heap Library, Version 8 General Notes ------------- Bios Settings Hardware Prefetch enabled Memory Array set to High-Performance Memory Array Base Compiler Invocation ------------------------ C benchmarks: icl -Qvc7.1 -Qc99 C++ benchmarks: icl -Qvc7.1 Base Portability Flags ---------------------- 403.gcc: -DSPEC_CPU_WIN32 464.h264ref: -DSPEC_CPU_NO_INTTYPES -DWIN32 Base Optimization Flags ----------------------- C benchmarks: -fast /F512000000 shlw32m.lib -link /FORCE:MULTIPLE C++ benchmarks: -fast -Qcxx_features /F512000000 shlw32m.lib -link /FORCE:MULTIPLE Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags file that was used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.01.html You can also download the XML flags source by saving the following link: http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090715.01.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2014 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.0. Report generated on Tue Jul 22 10:13:14 2014 by CPU2006 ASCII formatter v6932. Originally published on 25 January 2007.