SPEC(R) CINT2006 Summary IBM Corporation IBM BladeCenter HS21 XM (Intel Xeon E5310) Fri Jan 6 08:26:59 2006 CPU2006 License: 11 Test date: Jan-2007 Test sponsor: IBM Corporation Hardware availability: Feb-2007 Tested by: IBM Corporation Software availability: Aug-2006 Base Base Base Peak Peak Peak Benchmarks Ref. Run Time Ratio Ref. Run Time Ratio -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 9770 829 11.8 S 400.perlbench 9770 829 11.8 S 400.perlbench 9770 829 11.8 * 401.bzip2 9650 1136 8.49 S 401.bzip2 9650 1136 8.49 * 401.bzip2 9650 1136 8.49 S 403.gcc 8050 1042 7.73 S 403.gcc 8050 1042 7.72 S 403.gcc 8050 1042 7.72 * 429.mcf 9120 730 12.5 S 429.mcf 9120 730 12.5 S 429.mcf 9120 730 12.5 * 445.gobmk 10490 989 10.6 * 445.gobmk 10490 989 10.6 S 445.gobmk 10490 990 10.6 S 456.hmmer 9330 1377 6.77 S 456.hmmer 9330 1377 6.77 * 456.hmmer 9330 1377 6.77 S 458.sjeng 12100 1213 9.98 S 458.sjeng 12100 1213 9.98 * 458.sjeng 12100 1213 9.98 S 462.libquantum 20720 1916 10.8 S 462.libquantum 20720 1916 10.8 * 462.libquantum 20720 1916 10.8 S 464.h264ref 22130 1315 16.8 S 464.h264ref 22130 1314 16.8 * 464.h264ref 22130 1314 16.8 S 471.omnetpp 6250 763 8.19 S 471.omnetpp 6250 763 8.19 * 471.omnetpp 6250 763 8.19 S 473.astar 7020 898 7.82 S 473.astar 7020 899 7.81 * 473.astar 7020 899 7.81 S 483.xalancbmk 6900 551 12.5 S 483.xalancbmk 6900 551 12.5 S 483.xalancbmk 6900 551 12.5 * ============================================================================== 400.perlbench 9770 829 11.8 * 401.bzip2 9650 1136 8.49 * 403.gcc 8050 1042 7.72 * 429.mcf 9120 730 12.5 * 445.gobmk 10490 989 10.6 * 456.hmmer 9330 1377 6.77 * 458.sjeng 12100 1213 9.98 * 462.libquantum 20720 1916 10.8 * 464.h264ref 22130 1314 16.8 * 471.omnetpp 6250 763 8.19 * 473.astar 7020 899 7.81 * 483.xalancbmk 6900 551 12.5 * SPECint(R)_base2006 10.0 SPECint2006 Not Run HARDWARE -------- CPU Name: Intel Xeon E5310 CPU Characteristics: 1066MHz system bus CPU MHz: 1600 FPU: Integrated CPU(s) enabled: 8 cores, 2 chips, 4 cores/chip CPU(s) orderable: 1,2 chips Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 8 MB I+D on chip per chip, 4 MB shared / 2 cores L3 Cache: None Other Cache: None Memory: 16 GB (8 x 2GB DDR2-5300F ECC) Disk Subsystem: 1 x 74 GB SAS, 1000 RPM Other Hardware: None SOFTWARE -------- Operating System: Microsoft Windows Server 2003 Enterprise x64 Edition + SP1 (64-bit) Compiler: Intel C++ Compiler for IA32 version 9.1 Build no 20060816 Microsoft Visual Studio .Net 2003 (for libraries) Auto Parallel: No File System: NTFS System State: Default Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: Smart Heap Library, Version 8 Base Compiler Invocation ------------------------ C benchmarks: icl -Qvc7.1 -Qc99 C++ benchmarks: icl -Qvc7.1 Base Portability Flags ---------------------- 403.gcc: -DSPEC_CPU_WIN32 464.h264ref: -DSPEC_CPU_NO_INTTYPES -DWIN32 Base Optimization Flags ----------------------- C benchmarks: -fast /F512000000 shlw32m.lib -link /FORCE:MULTIPLE C++ benchmarks: -fast -Qcxx_features /F512000000 shlw32m.lib -link /FORCE:MULTIPLE Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags file that was used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090714.html You can also download the XML flags source by saving the following link: http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090714.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2014 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.0. Report generated on Tue Jul 22 10:35:01 2014 by CPU2006 ASCII formatter v6932. Originally published on 6 March 2007.