# Invocation command line: # /scratch/SPEC2006/cpu2006/bin/runspec --rate 64 --flagsurl config/Intel-ic11.0-int-linux64-revE.xml -c Nehalem.cfg -o all int # output_root was not used for this run ############################################################################ # Invocation command line: # runspec --rate 8 -c ScMP.cfg int ############################################################################ tune = base PATHSEP = / check_md5 = 1 reportable = 1 teeout = 1 # flagsurl = http://www.spec.org/cpu2006/flags/Intel-ic11.0-int-linux64-revE.xml ############################################################################ # # These are listed as benchmark-tuning-extension-machine # ############################################################################ default=default=default=default: CC = icc CXX = icpc FC = ifort OBJ = .o submit= MYMASK=`printf '0x%x' \$((1<<\$SPECCOPYNUM))`; taskset \$MYMASK $command sw_peak_ptrsize = Not Applicable int=default: sw_base_ptrsize = 32-bit fp=default: sw_base_ptrsize = 64-bit ################### Portability Flags and Notes ############################ 400.perlbench=default: CPORTABILITY= -DSPEC_CPU_LINUX_IA32 403.gcc=default: EXTRA_CFLAGS= -Dalloca=_alloca 462.libquantum=default: CPORTABILITY= -DSPEC_CPU_LINUX 483.xalancbmk=default: CXXPORTABILITY= -DSPEC_CPU_LINUX fp=default: PORTABILITY = -DSPEC_CPU_LP64 435.gromacs=default: LDPORTABILITY= -nofor_main 436.cactusADM=default: LDPORTABILITY= -nofor_main 454.calculix=default: LDPORTABILITY= -nofor_main 481.wrf=default: CPORTABILITY= -DSPEC_CPU_LINUX -DSPEC_CPU_CASE_FLAG # Tuning Flags ################################################################ # Base tuning default optimization # Feedback directed optimization not allowed in baseline for CPU2006 # However there is no limit on the number of flags as long as the same # flags are used in the same order for all benchmarks of a given language int=base=default=default: COPTIMIZE= -xSSE4.2 -ipo -O3 -no-prec-div -inline-calloc -opt-malloc-options=3 -opt-prefetch CXXOPTIMIZE= -xSSE4.2 -ipo -O3 -no-prec-div -opt-prefetch fp=base=default=default: OPTIMIZE= -xSSE4.2 -ipo -O3 -no-prec-div ################################################################# # (Edit this to match your system) ################################################################# default=default=default=default: license_num = 2929 test_sponsor = ScaleMP hw_avail = Apr-2009 sw_avail = Apr-2009 tester = ScaleMP hw_cpu_name = Intel Xeon X5570 hw_cpu_char = Intel Turbo Boost Technology is not-enabled hw_cpu_mhz = 2933 hw_disk = 4 x 1 x 500 GB SATA, 7200 RPM hw_fpu = Integrated hw_memory = 96 GB (4 x 12 x 2 GB DDR3-1333R, ECC, CL9) hw_model = vSMP Foundation (Intel Xeon X5570, see notes) hw_ncpuorder = 4,6,8,10,12,14,16,18,20,22,24,26,28,30,32 chips hw_ncores = 32 hw_nchips = 8 hw_ncoresperchip = 4 hw_nthreadspercore = 2 hw_other = InfiniBand hw_pcache = 32 KB I + 32 KB D on chip per core hw_scache = 256 KB I+D on chip per core hw_tcache = 8 MB I+D on chip per chip hw_ocache = 6 GB I+D off chip per entire system (see notes) hw_vendor = ScaleMP prepared_by = ScaleMP sw_file = xfs sw_os000 = Red Hat Enterprise Linux Server sw_os001 = release 5.3 (Tikanga) sw_os002 = Kernel: 2.6.27.19-1.vSMP sw_state = Multi-user, run level 3 sw_other = ScaleMP vSMP Foundation 2.0.44.0 int=default=default=default: sw_compiler000 = Intel C Compiler for applications running on sw_compiler001 = IA-32, Version 11.0.074 sw_compiler002 = Intel Fortran Compiler for applications running on sw_compiler003 = IA-32, Version 11.0.074 fp=default=default=default: sw_compiler000 = Intel C Compiler for applications running on sw_compiler001 = Intel 64, Version 11.0.074 sw_compiler002 = Intel Fortran Compiler for applications running on sw_compiler003 = Intel 64, Version 11.0.074 default: notes_plat_000 = ScaleMP notes_plat_005 = vSMP Foundation: 2.0.44.0 notes_plat_010 = Other Cache: notes_plat_015 = ScaleMP vSMP Foundation manages cache coherency between the notes_plat_020 = InfiniBand-connected systems via multiple concurrent memory notes_plat_025 = coherency mechanisms, on a per-block basis, based on notes_plat_030 = real-time memory activity access patterns. notes_plat_035 = This mechanism reserves 6 GB of the main memory across all notes_plat_040 = boards (distributed), which is used as a 4th level cache. notes_plat_045 = Hardware Details: notes_plat_050 = System was aggregated using 4 X SuperMicro SuperServer 6026T-NTR+. notes_plat_055 = The servers were connected with Melanox InfiniBand QDR and a notes_plat_060 = QDR switch. notes_plat_065 = CPU Characteristics: Intel Turbo Boost Technology not-enabled: notes_plat_070 = As the prerequisites listed below for enablement of this notes_plat_075 = technology did not exist. notes_plat_080 = The prerequisites for Turbo Boost Technology are: notes_plat_085 = - Hardware: Enabling Turbo Boost Technology require BIOS setting. notes_plat_090 = - Software: OS needs to be ACPI-aware and set P0 power state. # The following section was added automatically, and contains settings that # did not appear in the original configuration file, but were added to the # raw file after the run. default: flagsurl000 = http://www.spec.org/cpu2006/flags/Intel-ic11.0-int-linux64-revE.20090925.xml notes_submit_000 =The config file option 'submit' was used with taskset notes_submit_005 =to bind processes to cores