CPU2006 Flag Description
Dell Inc. Dell Precision T7500 (Intel Xeon W5590, 3.33 GHz)


Base Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C


Peak Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C


Base Portability Flags

410.bwaves

416.gamess

433.milc

434.zeusmp

435.gromacs

436.cactusADM

437.leslie3d

444.namd

447.dealII

450.soplex

453.povray

454.calculix

459.GemsFDTD

465.tonto

470.lbm

481.wrf

482.sphinx3


Peak Portability Flags

410.bwaves

416.gamess

433.milc

434.zeusmp

435.gromacs

436.cactusADM

437.leslie3d

444.namd

447.dealII

450.soplex

453.povray

454.calculix

459.GemsFDTD

465.tonto

470.lbm

481.wrf

482.sphinx3


Base Optimization Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C


Peak Optimization Flags

C benchmarks

433.milc

470.lbm

482.sphinx3

C++ benchmarks

444.namd

447.dealII

450.soplex

453.povray

Fortran benchmarks

410.bwaves

416.gamess

434.zeusmp

437.leslie3d

459.GemsFDTD

465.tonto

Benchmarks using both Fortran and C

435.gromacs

436.cactusADM

454.calculix

481.wrf


Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.


System and Other Tuning Information

Platform settings

One or more of the following settings may have been set. Please see the Notes section of the report to determine which, if any, have been modified.

Adjacent Cache Line Prefetch:

This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within an 128-byte sector that contains the data needed due to a cache line miss.

In some limited cases, setting this option from the Default may improve performance. In the majority of cases, the default setting provides better performance. Users should modify this option after performing application benchmarking to verify improved performance in their environment.

Hardware Prefetch:

This BIOS option allows allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern recognition algorithm.

In some limited cases, setting this option to Disabled may improve performance. In the majority of cases, the option set to Enabled provides better performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Hyper-Threading Technology

This BIOS setting disables/enables Hyper-Threading (HT) Technology. HT enables the processor to allocate an additional thread to a core.

Memory Node Interleaving

This BIOS setting when set to NUMA (Non-Uniform Memory Access) configures the system memory into blocks local to each processor. A NUMA-aware operating system can use this configuration to intelligently allocate memory for optimal performance.


Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags file that was used to format this result can be browsed at
http://www.spec.org/cpu2006/flags/dell.flags.ic11.0.win.html.

You can also download the XML flags source by saving the following link:
http://www.spec.org/cpu2006/flags/dell.flags.ic11.0.win.xml.


For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2006-2014 Standard Performance Evaluation Corporation
Tested with SPEC CPU2006 v1.1.
Report generated on Wed Jul 23 02:44:20 2014 by SPEC CPU2006 flags formatter v6906.