CPU2006 Flag Description
Acer Incorporated Gateway GW2000h-GW170h F1 (Intel Xeon X5660, 2.80 GHz)

This result has been formatted using multiple flags files. The "default header section" from each of them appears next.


Default header section from Intel-ic12.0-linux64-revB

SPEC CPU2006 Flag Description for the Intel(R) C++ and Fortran Compiler 12.0 for IA32 and Intel 64 applications

Copyright © 2006 Intel Corporation. All Rights Reserved.


Default header section from Acer-Intel-Linux-Settings-flags

SPEC CPU2006 Software OS and BIOS tuning Descriptions Acer Intel-based systems applications

Copyright © 2007 Intel Corporation. All Rights Reserved.


Base Compiler Invocation

C benchmarks

C++ benchmarks


Peak Compiler Invocation

C benchmarks (except as noted below)

400.perlbench

401.bzip2

456.hmmer

458.sjeng

C++ benchmarks


Base Portability Flags

400.perlbench

462.libquantum

483.xalancbmk


Peak Portability Flags

400.perlbench

401.bzip2

456.hmmer

458.sjeng

462.libquantum

483.xalancbmk


Base Optimization Flags

C benchmarks

C++ benchmarks


Peak Optimization Flags

C benchmarks

400.perlbench

401.bzip2

403.gcc

429.mcf

445.gobmk

456.hmmer

458.sjeng

462.libquantum

464.h264ref

C++ benchmarks

471.omnetpp

473.astar

483.xalancbmk


Base Other Flags

C benchmarks

403.gcc


Peak Other Flags

C benchmarks

403.gcc


Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.


System and Other Tuning Information

Platform settings

One or more of the following settings may have been set. If so, the "Platform Notes" section of the report will say so; and you can read below to find out more about what these settings mean.

Fan Speed Control Modes (Default = Balanced/BL):

This feature allows the user to select the fan cooling solution for the system. Values for this BIOS setting can be:

Adjacent Cache Line Prefetch (Default = Enabled):

This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within an 128-byte sector that contains the data needed due to a cache line miss.

In some limited cases, setting this option to Disabled may improve performance. In the majority of cases, the default value of Enabled provides better performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Hardware Prefetcher (Default = Enabled):

This BIOS option allows allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern recognition algorithm.

In some limited cases, setting this option to Disabled may improve performance. In the majority of cases, the default value of Enabled provides better performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Data Reuse Optimization(Default = Enabled):

This BIOS option allows the enabling/disabling of the Data Reuse optimization.

Enabling this option reduces the frequency of L3 cache updates from the L1 cache. This may improve performance by reducing the internal bandwidth consumed by constantly updating L1 cache lines in the L3 cache.

Since this optimization results in more fetches to main memory, in some limited cases, setting this option to Disabled may improve performance. In the majority of cases, the default value of Enabled provides better performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Intel TurboMode tech (Default = Enabled):

Turbo Boost Technology is a processor feature which allows the processor to transition to a higher frequency than the processor's rate speed if the processor has available power headroom and is within tempereature specifications. Disabling this feature will reduce power usage but will reduce the system's maximum achievable performance under some workloads.

Memory Frequency (Default=Auto)

Sets the memory speed setting for system. Values for this BIOS setting can be:

SATA #1 Controller (Default=Auto)

Sets the mode for the embedded controller. The values for this BIOS setting can be:

submit= MYMASK=`printf '0x%x' \$((1<<\$SPECCOPYNUM))`; /usr/bin/taskset \$MYMASK $command

When running multiple copies of benchmarks, the SPEC config file feature submit is sometimes used to cause individual jobs to be bound to specific processors. This specific submit command is used for Linux. The description of the elements of the command are:

Using numactl to bind processes and memory to cores

For multi-copy runs or single copy runs on systems with multiple sockets, it is advantageous to bind a process to a particular core. Otherwise, the OS may arbitrarily move your process from one core to another. This can effect performance. To help, SPEC allows the use of a "submit" command where users can specify a utility to use to bind processes. We have found the utility 'numactl' to be the best choice.

numactl runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a command and inherited by all of its children. The numactl flag "--physcpubind" specifies which core(s) to bind the process. "-l" instructs numactl to keep a process memory on the local node while "-m" specifies which node(s) to place a process memory. For full details on using numactl, please refer to your Linux documentation, 'man numactl'

mysubmit.pl

This perl script is used to ensure that for a system with N cores the first N/2 benchmark copies are bound to a core that does not share its L2 cache with any of the other copies. The script does this by retrieving and using CPU data from /proc/cpuinfo. Note this script will only work for 6-core CPUs.

ulimit -s [n | unlimited] (Linux)

Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.

KMP_STACKSIZE=integer[B|K|M|G|T] (Linux)

Sets the number of bytes to allocate for each parallel thread to use as its private stack. Use the optional suffix B, K, M, G, or T, to specify bytes, kilobytes, megabytes, gigabytes, or terabytes. The default setting is 2M on IA32 and 4M on IA64.

KMP_AFFINITY=physical,n (Linux)

Assigns threads to consecutive physical processors (for example, cores), beginning at processor n. Specifies the static mapping of user threads to physical cores, beginning at processor n. For example, if a system is configured with 8 cores, and OMP_NUM_THREADS=8 and KMP_AFFINITY=physical,2 are set, then thread 0 will mapped to core 2, thread 1 will be mapped to core 3, and so on in a round-robin fashion.

OMP_NUM_THREADS=n

This Environment Variable sets the maximum number of threads to use for OpenMP* parallel regions to n if no other value is specified in the application. This environment variable applies to both -openmp and -parallel (Linux) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores:
export OMP_NUM_THREADS=8
Default is the number of cores visible to the OS.

vm.max_map_count-n (Linux)

The maximum number of memory map areas a process may have. Memory map areas are used as a side-effect of calling malloc, directly by mmap and mprotect, and also when loading shared libraries.


Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2006/flags/Intel-ic12.0-linux64-revB.html,
http://www.spec.org/cpu2006/flags/Acer-Intel-Linux-Settings-flags.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2006/flags/Intel-ic12.0-linux64-revB.xml,
http://www.spec.org/cpu2006/flags/Acer-Intel-Linux-Settings-flags.xml.


For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2006-2014 Standard Performance Evaluation Corporation
Tested with SPEC CPU2006 v1.1.
Report generated on Wed Jul 23 21:33:59 2014 by SPEC CPU2006 flags formatter v6906.