CPU2006 Flag Description
NEC Corporation Express5800/R120b-2 (Intel Xeon X5650)

This result has been formatted using multiple flags files. The "default header section" from each of them appears next.


Default header section from Intel-ic12.0-linux64-revB

SPEC CPU2006 Flag Description for the Intel(R) C++ and Fortran Compiler 12.0 for IA32 and Intel 64 applications

Copyright © 2006 Intel Corporation. All Rights Reserved.


Default header section from NEC-Intel-Linux-Settings-flags-revF

SPEC CPU2006 Software OS and BIOS tuning Descriptions NEC Express5800 Intel-based systems applications

Copyright © 2007 Intel Corporation. All Rights Reserved.


Base Compiler Invocation

C benchmarks

C++ benchmarks


Peak Compiler Invocation

C benchmarks (except as noted below)

400.perlbench

429.mcf

445.gobmk

464.h264ref

C++ benchmarks (except as noted below)

473.astar


Base Portability Flags

400.perlbench

401.bzip2

403.gcc

429.mcf

445.gobmk

456.hmmer

458.sjeng

462.libquantum

464.h264ref

471.omnetpp

473.astar

483.xalancbmk


Peak Portability Flags

400.perlbench

401.bzip2

403.gcc

456.hmmer

458.sjeng

462.libquantum

473.astar

483.xalancbmk


Base Optimization Flags

C benchmarks

C++ benchmarks


Peak Optimization Flags

C benchmarks

400.perlbench

401.bzip2

403.gcc

429.mcf

445.gobmk

456.hmmer

458.sjeng

462.libquantum

464.h264ref

C++ benchmarks

471.omnetpp

473.astar

483.xalancbmk


Base Other Flags

C benchmarks

403.gcc


Peak Other Flags

C benchmarks

403.gcc


Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.


System and Other Tuning Information

Platform settings

One or more of the following settings may have been set. If so, the "General Notes" section of the report will say so; and you can read below to find out more about what these settings mean.

KMP_STACKSIZE

Specify stack size to be allocated for each thread.

KMP_AFFINITY

KMP_AFFINITY = < physical | logical >, starting-core-id
specifies the static mapping of user threads to physical cores. For example, if you have a system configured with 8 cores, OMP_NUM_THREADS=8 and KMP_AFFINITY=physical,0 then thread 0 will mapped to core 0, thread 1 will be mapped to core 1, and so on in a round-robin fashion.

KMP_AFFINITY = granularity=fine,scatter
The value for the environment variable KMP_AFFINITY affects how the threads from an auto-parallelized program are scheduled across processors.
Specifying granularity=fine selects the finest granularity level, causes each OpenMP thread to be bound to a single thread context.
This ensures that there is only one thread per core on cores supporting HyperThreading Technology
Specifying scatter distributes the threads as evenly as possible across the entire system.
Hence a combination of these two options, will spread the threads evenly across sockets, with one thread per physical core.

OMP_NUM_THREADS

Sets the maximum number of threads to use for OpenMP* parallel regions if no other value is specified in the application. This environment variable applies to both -openmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores: export OMP_NUM_THREADS=8

Server Class:

This BIOS option sets "Hardware Prefetcher", "Adjacent Cache Line Prefetch", "L1 Data Prefetcher" and "Data Reuse Optimization". This default setting is "HPC".

If set to "HPC", each BIOS option set as follows:
- Hardware Prefetcher: Enabled
- Adjacent Cache Line Prefetch: Enabled
- L1 Data Prefetcher: Enabled
- Data Reuse Optimization: Enabled.
If set to "Enterprise", each BIOS option set as follows:
- Hardware Prefetcher: Disabled
- Adjacent Cache Line Prefetch: Disabled
- L1 Data Prefetcher: Disabled
- Data Reuse Optimization: Enabled.
If set to "Custom", it is possible to set each BIOS option which are initialized to their default setting.

Hardware Prefetcher:

This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm. This default setting is "Enabled".

In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Adjacent Cache Line Prefetch:

This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within a 128-byte sector that contains the data needed due to a cache line miss. This default setting is "Enabled".

In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

L1 Data Prefetcher:

This BIOS option allows enabling/disabling the function of Data Cache Unit (DCU) Streamer prefetcher. This default setting is "Enabled".

If this option sets to "Enabled", when the DCU Streamer prefetcher detects multiple loads from the same line done within a time limit, it prefetches the next line into the L1 data cache.

Data Reuse Optimization:

Enabling this BIOS option reduces the frequency of L3 cache updates from L1. This default setting is "Enabled".

This may improve performance by reducing the internal bandwidth consumed by constantly updating L1 cache lines in L3.

Since this results in more fetches to main memory, setting this option to Disabled may improve performance in some cases. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Performance/Watt:

This BIOS option sets the turbo boost engagement after the maximum power state (P0).

If set to Traditional this will be less than 2 seconds to provide maximum performance, otherwise P0 restained for more than 2 seconds. This setting is able to set to "Traditional" or "Power Optimized" in BIOS. This default setting is "Power Optimized".

FSB High Bandwidth Optimization:

Enabling this option allows the chipset to defer memory transactions and process them out of order for optimal performance.

Hyper-Threading Technology:

Disabling Intel's Hyper-Threading Technology reduces the number of threads per core to 1. The default is Enabled; in this case each core provides additional resources for executing up to 2 threads in parallel.

Patrol Scrubbing:

This is a background activity initiated by the processor to seek out and fix memory errors. Patrol Scrub scans all of memory doing simulated "READs" while checking for ECC errors. If any ECC errors are detected during this process, they are logged as Patrol errors. Correctable errors are corrected and written back into memory. This mode is able to set to "Enable" or "Disable" in BIOS.

Memory Voltage:

If set to "Normal" the system supplies 1.5V in memory, otherwise the system supplies 1.35V in memory. This setting is able to set to "Low" or "Normal" in BIOS. This default setting is "Low".

NUMA configuration:

This BIOS option allows enabling/disabling the support of Non-Uniform Memory Access (NUMA). In NUMA mode, physical memory addresses are divided between nodes at a large grain and resource allocation tables describing this division are presented to the operating system.

For example, on a two-node system, if both nodes are configured with 6GB of memory, physical memory addresses 0 - 6GB-1 map to one node and addresses 6GB-12GB-1 map to the other node. To make use of this, the operating system needs to be NUMA-aware and can then try to optimize access to the processor's local memory.

In Non-NUMA mode (NUMA configuration set to disabled), the memory is interleaved across the CPUs. Non-NUMA mode may lead to more balanced but generally reduced performance for bandwidth-sensitive applications.

ulimit -s <n>

Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.

submit= MYMASK=`printf '0x%x' $((1<<$SPECCOPYNUM))`; /usr/bin/taskset $MYMASK $command

When running multiple copies of benchmarks, the SPEC config file feature submit is sometimes used to cause individual jobs to be bound to specific processors. This specific submit command is used for Linux. The description of the elements of the command are:

Using numactl to bind processes and memory to cores

For multi-copy runs or single copy runs on systems with multiple sockets, it is advantageous to bind a process to a particular core. Otherwise, the OS may arbitrarily move your process from one core to another. This can affect performance. To help, SPEC allows the use of a "submit" command where users can specify a utility to use to bind processes. We have found the utility 'numactl' to be the best choice.

numactl runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a command and inherited by all of its children. The numactl flag "--physcpubind" specifies which core(s) to bind the process. "-l" instructs numactl to keep a process memory on the local node while "-m" specifies which node(s) to place a process memory. For full details on using numactl, please refer to your Linux documentation, 'man numactl'

submit= $[top]/mysubmit.pl $SPECCOPYNUM "$command"

On Xeon 74xx series processors, some benchmarks at peak will run n/2 copies on a system with n logical processors. The mysubmit.pl script assigns each copy in such a way that no two copies will share an L2 cache, for optimal performance. The script looks in /proc/cpuinfo to come up with the list of cores that will satisfy this requirement. The source code is shown below.

Source ******************************************************************************************************


#!/usr/bin/perl
 
use strict;
use Cwd;
 
# The order in which we want copies to be bound to cores
# Copies: 0, 1, 2, 3
# Cores:  0, 1, 3, 6
 
my $rundir        = getcwd;
 
my $copynum = shift @ARGV;

my $i;
my $j;
my $tag;
my $num;
my $core;
my $numofcores; 

my @proc;
my @cores;

open(INPUT, "/proc/cpuinfo") or
   die "can't open /proc/cpuinfo\n"; 

#open(OUTPUT, "STDOUT");

# proc[i][0] = logical processor ID
# proc[i][1] = physical processor ID
# proc[i][2] = core ID

$i = 0;
$numofcores = 0;

while(<INPUT>)
{
  chop;
 
  ($tag, $num) = split(/\s+:\s+/, $_);


  if ($tag eq "processor") {
      $proc[$i][0] = $num;
  }

  if ($tag eq "physical id") {
      $proc[$i][1] = $num;
  }

  if ($tag eq "core id") {
      $proc[$i][2] = $num;
      $i++;
      $numofcores++;
  }
}

$i = 0;
$j = 0;

for $core (0, 4, 2, 1, 5, 3) {
  while ($i < $numofcores) {
     if ($proc[$i][2] == $core) {
        $cores[$j] = $proc[$i][0];
        $j++;
     }
     $i++;
  }
  $i=0;
}

open  RUNCOMMAND, "> runcommand" or die "failed to create run file";
print RUNCOMMAND "cd $rundir\n";
print RUNCOMMAND "@ARGV\n";
close RUNCOMMAND;
system 'taskset', '-c', $cores[$copynum], 'sh', "$rundir/runcommand";


Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2006/flags/Intel-ic12.0-linux64-revB.html,
http://www.spec.org/cpu2006/flags/NEC-Intel-Linux-Settings-flags-revF.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2006/flags/Intel-ic12.0-linux64-revB.xml,
http://www.spec.org/cpu2006/flags/NEC-Intel-Linux-Settings-flags-revF.xml.


For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2006-2014 Standard Performance Evaluation Corporation
Tested with SPEC CPU2006 v1.1.
Report generated on Wed Jul 23 21:23:16 2014 by SPEC CPU2006 flags formatter v6906.