SPEC(R) CINT2006 Summary SGI SGI UV 2000 (Intel Xeon E5-4650, 2.7 GHz) Sat Sep 22 00:27:23 2012 CPU2006 License: 4 Test date: Sep-2012 Test sponsor: SGI Hardware availability: Jun-2012 Tested by: SGI Software availability: Jul-2012 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 2032 797 24900 S 400.perlbench 2032 802 24800 * 400.perlbench 2032 802 24800 S 401.bzip2 2032 1081 18100 * 401.bzip2 2032 1080 18200 S 401.bzip2 2032 1082 18100 S 403.gcc 2032 889 18400 S 403.gcc 2032 904 18100 S 403.gcc 2032 903 18100 * 429.mcf 2032 494 37500 S 429.mcf 2032 496 37400 * 429.mcf 2032 497 37300 S 445.gobmk 2032 932 22900 S 445.gobmk 2032 931 22900 S 445.gobmk 2032 932 22900 * 456.hmmer 2032 406 46700 S 456.hmmer 2032 407 46600 * 456.hmmer 2032 407 46600 S 458.sjeng 2032 984 25000 S 458.sjeng 2032 987 24900 S 458.sjeng 2032 986 24900 * 462.libquantum 2032 187 226000 * 462.libquantum 2032 187 225000 S 462.libquantum 2032 186 226000 S 464.h264ref 2032 1088 41300 S 464.h264ref 2032 1094 41100 S 464.h264ref 2032 1093 41100 * 471.omnetpp 2032 760 16700 * 471.omnetpp 2032 760 16700 S 471.omnetpp 2032 759 16700 S 473.astar 2032 641 22300 S 473.astar 2032 642 22200 S 473.astar 2032 641 22200 * 483.xalancbmk 2032 487 28800 S 483.xalancbmk 2032 488 28800 * 483.xalancbmk 2032 488 28700 S ============================================================================== 400.perlbench 2032 802 24800 * 401.bzip2 2032 1081 18100 * 403.gcc 2032 903 18100 * 429.mcf 2032 496 37400 * 445.gobmk 2032 932 22900 * 456.hmmer 2032 407 46600 * 458.sjeng 2032 986 24900 * 462.libquantum 2032 187 226000 * 464.h264ref 2032 1093 41100 * 471.omnetpp 2032 760 16700 * 473.astar 2032 641 22200 * 483.xalancbmk 2032 488 28800 * SPECint(R)_rate_base2006 31100 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon E5-4650 CPU Characteristics: Intel Turbo Boost Technology disabled CPU MHz: 2700 FPU: Integrated CPU(s) enabled: 1024 cores, 128 chips, 8 cores/chip, 2 threads/core CPU(s) orderable: 4-256 chips Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 256 KB I+D on chip per core L3 Cache: 20 MB I+D on chip per chip Other Cache: None Memory: 8 TB (1024 x 8 GB 2Rx4 PC3-12800R-11, ECC) Disk Subsystem: 8 TB tmpfs Other Hardware: NUMAlink6 routers SOFTWARE -------- Operating System: SUSE Linux Enterprise Server 11 (x86_64) SP2, Kernel 3.0.38-0.5-default Compiler: C/C++: Version 12.1.3.293 of Intel C++ Studio XE for Linux Auto Parallel: No File System: tmpfs System State: Run Level 3 (multi-user) Base Pointers: 32/64-bit Peak Pointers: Not Applicable Other Software: Microquill SmartHeap V8 SGI Accelerate 1.4, Patch 10920 SGI Foundation Software 2.6, Patch 10931 Submit Notes ------------ The dplace mechanism was used to bind copies to processors. The config file option 'submit' was used to generate dplace commands to bind each copy to a specific processor. Benchmark copies were launched in a staggered fashion to minimize kernel contention associated with synchronized launches. For details, please see the config file. Operating System Notes ---------------------- Tmpfs filesystem set up with: mount -t tmpfs -o size=8192g,rw tmpfs /mnt/shm/ Stack size set to unlimited using "ulimit -s unlimited" sysctl vm.stat_interval=10 Platform Notes -------------- SGI BIOS version 3.0.7 General Notes ------------- Environment variables set by runspec before the start of the run: LD_LIBRARY_PATH = "/mnt/shm/cpu2006-1.2/libs/32:/mnt/shm/cpu2006-1.2/libs/64" Binaries compiled on a system with 2x Xeon E5540 CPU + 32GB memory using SLES11 SP1 Transparent Huge Pages enabled with: echo always > /sys/kernel/mm/transparent_hugepage/enabled Filesystem page cache cleared with: echo 1 > /proc/sys/vm/drop_caches Base Compiler Invocation ------------------------ C benchmarks: icc -m64 C++ benchmarks: icpc -m64 Base Portability Flags ---------------------- 400.perlbench: -DSPEC_CPU_LP64 -DSPEC_CPU_LINUX_X64 401.bzip2: -DSPEC_CPU_LP64 403.gcc: -DSPEC_CPU_LP64 429.mcf: -DSPEC_CPU_LP64 445.gobmk: -DSPEC_CPU_LP64 456.hmmer: -DSPEC_CPU_LP64 458.sjeng: -DSPEC_CPU_LP64 462.libquantum: -DSPEC_CPU_LP64 -DSPEC_CPU_LINUX 464.h264ref: -DSPEC_CPU_LP64 471.omnetpp: -DSPEC_CPU_LP64 473.astar: -DSPEC_CPU_LP64 483.xalancbmk: -DSPEC_CPU_LP64 -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -xAVX -ipo -O3 -no-prec-div -auto-p32 -opt-prefetch -opt-mem-layout-trans=3 C++ benchmarks: -xAVX -ipo -O3 -no-prec-div -auto-p32 -opt-prefetch -opt-mem-layout-trans=3 -Wl,-z,muldefs -L/store/jbaron/cpu2006-1.2/SmartHeap_8/lib -lsmartheapC64 -lsmartheap64 Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic12.1-official-linux64.20120912.html http://www.spec.org/cpu2006/flags/SGI-platform.20121009.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2006/flags/Intel-ic12.1-official-linux64.20120912.xml http://www.spec.org/cpu2006/flags/SGI-platform.20121009.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2014 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.2. Report generated on Thu Jul 24 12:52:15 2014 by CPU2006 ASCII formatter v6932. Originally published on 9 October 2012.