| Compilers |
Oracle Solaris Studio 12.3
|
|---|---|
| Operating systems: | Solaris 10 and 11 |
| Copyright: |
The text for many of the descriptions below was excerpted from the Solaris Studio Compiler Documentation, which is copyright © 2013 Oracle Corporation. The original documentation can be found at http://www.oracle.com/technetwork/indexes/documentation/. |
![[user]](http://www.spec.org/auto/cpu2006/flags/user.png)
Invoke the Oracle Solaris Studio C Compiler.
Invoke the Oracle Solaris Studio C++ Compiler
Invoke the Oracle Solaris Studio Fortran 90 Compiler
Invoke the Oracle Solaris Studio C Compiler.
Invoke the Oracle Solaris Studio C++ Compiler
Invoke the Oracle Solaris Studio Fortran 90 Compiler
A convenience option, this switch selects several other options that are described in this file.
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Allows the compiler to perform type-based alias analysis at the specified alias level:
Control the level of searching that the compiler does for prefetch opportunities by setting n to 1, 2, or 3, where higher numbers mean to do more searching. The default for Oracle Solaris Studio C and Oracle Solaris Studio C++ is 1. The default for Oracle Solaris Studio Fortran is 2.
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Links in a library of general purpose memory allocation routines which can be faster than those found in libc, at the expense of more virtual memory consumed.
A convenience option, this switch selects several other options that are described in this file.
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Allows the compiler to perform type-based alias analysis:
Disables use of the compiler-provided Cstd header files and the STLport's Standard Library implementation.
Adds the directory for the Apache C++ Standard Library include files to the search path at compile time.
Adds the directory for the Apache C++ Standard Library include files to the search path at compile time.
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Adds the directory for the Apache C++ Standard Library to the search path at link time
Specifies library search directory for the Apache C++ Standard Library for use by the runtime linker. The information is recorded in the object file and passed to the runtime linker.
Link with the Apache C++ Standard Library ("stdcxx"). The conventions for naming libraries are described in the README that comes with stdcxx; for example, "std8D" indicates a 64-bit shared library with optimization enabled; "std8d" is a 32-bit shared library with optimization enabled.
A convenience option, this switch selects the following switches that are described in this file:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Allow the compiler to transform math library calls within loops into calls to the vector math library. Specifying
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
A convenience option, this switch selects several other options that are described in this file.
A convenience option, this switch selects the following switches that are described in this file:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Allows the compiler to perform type-based alias analysis at the specified alias level:
Control the level of searching that the compiler does for prefetch opportunities by setting n to 1, 2, or 3, where higher numbers mean to do more searching. The default for Oracle Solaris Studio C and Oracle Solaris Studio C++ is 1. The default for Oracle Solaris Studio Fortran is 2.
Allow the compiler to transform math library calls within loops into calls to the vector math library. Specifying
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
A convenience option, this switch selects several other options that are described in this file.
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Allows the compiler to perform type-based alias analysis at the specified alias level:
Controls simplifying assumptions for floating point arithmetic:
[optimizer flag]
Inliner only considers routines smaller than n pseudo instructions as possible inline candidates.
[code generator flag]
Specifies that all loops can be pipelined without needing to be concerned about loop-carried dependencies.
[code generator flag]
During Expansion (that is, prior to register allocation), use the 'movcc' instruction to implement min and max operations. The options for use of movcc include:
If the "Ex" is followed by the optional character "1", then movcc will be applied during the first phase of peephole optimization, but not during later phases.
[code generator flag]
Allow the pipeliner to unroll multi-instruction loops that set integer condition codes
Structure Array Contraction reduces strides in a hot loop accessing a big array. This is done by collecting only the hot fields into a new structure and rearranging the dimensions in the new array (of the new structure) to minimize stride width, e.g. a[x][y] to a[y][x]
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Collect profile data for feedback-directed optimization. If an option directory is named, the feedback will be stored there.
When FDO is used, the training run gathers information regarding execution paths and data values. Hardware performance counters are not used. FDO improves existing optimizations but does not introduce new classes of optimization.
Use data collected for profile feedback. If an option directory is named, look for the feedback data there.
A convenience option, this switch selects several other options that are described in this file.
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Allows the compiler to perform type-based alias analysis at the specified alias level:
Control the level of searching that the compiler does for prefetch opportunities by setting n to 1, 2, or 3, where higher numbers mean to do more searching. The default for Oracle Solaris Studio C and Oracle Solaris Studio C++ is 1. The default for Oracle Solaris Studio Fortran is 2.
Set the preferred page size for running the program.
Links in a linker mapfile that aligns text, data, and bss on 256 MB boundaries.
Links in a library of general purpose memory allocation routines which can be faster than those found in libc, at the expense of more virtual memory consumed.
Collect profile data for feedback-directed optimization. If an option directory is named, the feedback will be stored there.
When FDO is used, the training run gathers information regarding execution paths and data values. Hardware performance counters are not used. FDO improves existing optimizations but does not introduce new classes of optimization.
Use data collected for profile feedback. If an option directory is named, look for the feedback data there.
A convenience option, this switch selects several other options that are described in this file.
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Enable unrolling loops n times where possible.
Adjust the compiler's assumptions about prefetch latency by the specified factor. Typically values in the range of 0.5 to 2.0 will be useful. A lower number might indicate that data will usually be cache resident; a higher number might indicate a relatively larger gap between the processor speed and the memory speed (compared to the assumptions built into the compiler).
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Links in a library of general purpose memory allocation routines which can be faster than those found in libc, at the expense of more virtual memory consumed.
Collect profile data for feedback-directed optimization. If an option directory is named, the feedback will be stored there.
When FDO is used, the training run gathers information regarding execution paths and data values. Hardware performance counters are not used. FDO improves existing optimizations but does not introduce new classes of optimization.
Use data collected for profile feedback. If an option directory is named, look for the feedback data there.
A convenience option, this switch selects several other options that are described in this file.
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Allows the compiler to perform type-based alias analysis:
Control generation of prefetch instructions.
(Explicit prefetch macros are not used in the source code of the SPEC CPU2006 benchmarks; therefore, in the context of CPU2006, -xprefetch=yes is effectively a synonym for -xprefetch=auto.)
[code generator flag]
Specifies that all loops can be pipelined without needing to be concerned about loop-carried dependencies.
Use STLport's Standard Library implementation instead of the default libCstd.
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Collect profile data for feedback-directed optimization. If an option directory is named, the feedback will be stored there.
When FDO is used, the training run gathers information regarding execution paths and data values. Hardware performance counters are not used. FDO improves existing optimizations but does not introduce new classes of optimization.
Use data collected for profile feedback. If an option directory is named, look for the feedback data there.
A convenience option, this switch selects several other options that are described in this file.
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Allows the compiler to perform type-based alias analysis:
Treat pointer-valued function parameters as restricted pointers.
Control generation of prefetch instructions.
(Explicit prefetch macros are not used in the source code of the SPEC CPU2006 benchmarks; therefore, in the context of CPU2006, -xprefetch=yes is effectively a synonym for -xprefetch=auto.)
Disables use of the compiler-provided Cstd header files and the STLport's Standard Library implementation.
Adds the directory for the Apache C++ Standard Library include files to the search path at compile time.
Adds the directory for the Apache C++ Standard Library include files to the search path at compile time.
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Adds the directory for the Apache C++ Standard Library to the search path at link time
Specifies library search directory for the Apache C++ Standard Library for use by the runtime linker. The information is recorded in the object file and passed to the runtime linker.
Link with the Apache C++ Standard Library ("stdcxx"). The conventions for naming libraries are described in the README that comes with stdcxx; for example, "std8D" indicates a 64-bit shared library with optimization enabled; "std8d" is a 32-bit shared library with optimization enabled.
Collect profile data for feedback-directed optimization. If an option directory is named, the feedback will be stored there.
When FDO is used, the training run gathers information regarding execution paths and data values. Hardware performance counters are not used. FDO improves existing optimizations but does not introduce new classes of optimization.
Use data collected for profile feedback. If an option directory is named, look for the feedback data there.
A convenience option, this switch selects several other options that are described in this file.
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Use STLport's Standard Library implementation instead of the default libCstd.
Specify optimization level n:
Enable unrolling loops n times where possible.
Treat pointer-valued function parameters as restricted pointers.
[code generator flag]
Turns on prefetching for outer loops
[code generator flag]
Indicates to the compiler to insert n extra prefetches for each indirect access in outer loops
[code generator flag]
Insert indirect prefetches when the indirect access chain spans across basic blocks.
[optimizer flag]
Allow prefetching through up to n levels of indirect memory references.
Adjust the compiler's assumptions about prefetch latency by the specified factor. Typically values in the range of 0.5 to 2.0 will be useful. A lower number might indicate that data will usually be cache resident; a higher number might indicate a relatively larger gap between the processor speed and the memory speed (compared to the assumptions built into the compiler).
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Links in a library of general purpose memory allocation routines which can be faster than those found in libc, at the expense of more virtual memory consumed.
Collect profile data for feedback-directed optimization. If an option directory is named, the feedback will be stored there.
When FDO is used, the training run gathers information regarding execution paths and data values. Hardware performance counters are not used. FDO improves existing optimizations but does not introduce new classes of optimization.
Use data collected for profile feedback. If an option directory is named, look for the feedback data there.
A convenience option, this switch selects several other options that are described in this file.
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Specify optimization level n:
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Allows the compiler to perform type-based alias analysis:
Perform link-time optimizations on the resulting executable over and above any optimizations in the object files. These optimizations are performed at link time by analyzing the object binary code. The meanings of the options are:
0. The link optimizer is disabled. (This is the default.)
1. Perform optimizations based on control flow analysis, including instruction cache coloring and branch optimizations, at link time.
2. Perform additional data flow analysis, including dead-code elimination and address computation simplification, at link time.
Control generation of prefetch instructions.
(Explicit prefetch macros are not used in the source code of the SPEC CPU2006 benchmarks; therefore, in the context of CPU2006, -xprefetch=yes is effectively a synonym for -xprefetch=auto.)
Enable unrolling loops n times where possible.
[optimizer flag]
Inliner only considers routines smaller than n pseudo instructions as possible inline candidates.
[optimizer flag]
Control the optimizer's loop inliner; Set inline callee size limit to n. The unit roughly corresponds to the number of instructions.
[optimizer flag]
Control the optimizer's loop inliner; The inliner is allowed to increase the size of the program by up to n%.
[code generator flag]
During Expansion (that is, prior to register allocation), use the 'movcc' instruction to implement min and max operations. The options for use of movcc include:
If the "Ex" is followed by the optional character "1", then movcc will be applied during the first phase of peephole optimization, but not during later phases.
[code generator flag]
Allow the pipeliner to unroll multi-instruction loops that set integer condition codes
Use STLport's Standard Library implementation instead of the default libCstd.
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
This library provides faster versions of some common functions, such as malloc/free and bcopy.
Collect profile data for feedback-directed optimization. If an option directory is named, the feedback will be stored there.
When FDO is used, the training run gathers information regarding execution paths and data values. Hardware performance counters are not used. FDO improves existing optimizations but does not introduce new classes of optimization.
Use data collected for profile feedback. If an option directory is named, look for the feedback data there.
A convenience option, this switch selects the following switches that are described in this file:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Enable unrolling loops n times where possible.
Allow the compiler to transform math library calls within loops into calls to the vector math library. Specifying
Control generation of prefetch instructions.
(Explicit prefetch macros are not used in the source code of the SPEC CPU2006 benchmarks; therefore, in the context of CPU2006, -xprefetch=yes is effectively a synonym for -xprefetch=auto.)
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
A convenience option, this switch selects the following switches that are described in this file:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Control generation of prefetch instructions.
(Explicit prefetch macros are not used in the source code of the SPEC CPU2006 benchmarks; therefore, in the context of CPU2006, -xprefetch=yes is effectively a synonym for -xprefetch=auto.)
Enable unrolling loops n times where possible.
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
A convenience option, this switch selects the following switches that are described in this file:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Enable unrolling loops n times where possible.
Allow the compiler to transform math library calls within loops into calls to the vector math library. Specifying
Adjust the compiler's assumptions about prefetch latency by the specified factor. Typically values in the range of 0.5 to 2.0 will be useful. A lower number might indicate that data will usually be cache resident; a higher number might indicate a relatively larger gap between the processor speed and the memory speed (compared to the assumptions built into the compiler).
[code generator flag]
Specifies that all loops can be pipelined without needing to be concerned about loop-carried dependencies.
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Collect profile data for feedback-directed optimization. If an option directory is named, the feedback will be stored there.
When FDO is used, the training run gathers information regarding execution paths and data values. Hardware performance counters are not used. FDO improves existing optimizations but does not introduce new classes of optimization.
Use data collected for profile feedback. If an option directory is named, look for the feedback data there.
A convenience option, this switch selects the following switches that are described in this file:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Enable unrolling loops n times where possible.
Adjust the compiler's assumptions about prefetch latency by the specified factor. Typically values in the range of 0.5 to 2.0 will be useful. A lower number might indicate that data will usually be cache resident; a higher number might indicate a relatively larger gap between the processor speed and the memory speed (compared to the assumptions built into the compiler).
Control the level of searching that the compiler does for prefetch opportunities by setting n to 1, 2, or 3, where higher numbers mean to do more searching. The default for Oracle Solaris Studio C and Oracle Solaris Studio C++ is 1. The default for Oracle Solaris Studio Fortran is 2.
[code generator flag]
Control irregular loop prefetching; sets the prefetch look ahead distance, in bytes. The default is 256.
Disable loop unroll and jam optimization in iropt
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Collect profile data for feedback-directed optimization. If an option directory is named, the feedback will be stored there.
When FDO is used, the training run gathers information regarding execution paths and data values. Hardware performance counters are not used. FDO improves existing optimizations but does not introduce new classes of optimization.
Use data collected for profile feedback. If an option directory is named, look for the feedback data there.
A convenience option, this switch selects the following switches that are described in this file:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Specify optimization level n:
Enable unrolling loops n times where possible.
Control generation of prefetch instructions.
(Explicit prefetch macros are not used in the source code of the SPEC CPU2006 benchmarks; therefore, in the context of CPU2006, -xprefetch=yes is effectively a synonym for -xprefetch=auto.)
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Links in a library of general purpose memory allocation routines which can be faster than those found in libc, at the expense of more virtual memory consumed.
A convenience option, this switch selects several other options that are described in this file.
A convenience option, this switch selects the following switches that are described in this file:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Specify optimization level n:
Enable unrolling loops n times where possible.
Adjust the compiler's assumptions about prefetch latency by the specified factor. Typically values in the range of 0.5 to 2.0 will be useful. A lower number might indicate that data will usually be cache resident; a higher number might indicate a relatively larger gap between the processor speed and the memory speed (compared to the assumptions built into the compiler).
[code generator flag]
During Expansion (that is, prior to register allocation), use the 'movcc' instruction to implement min and max operations. The options for use of movcc include:
If the "Ex" is followed by the optional character "1", then movcc will be applied during the first phase of peephole optimization, but not during later phases.
[code generator flag]
Allow the pipeliner to unroll multi-instruction loops that set integer condition codes
Structure Array Contraction reduces strides in a hot loop accessing a big array. This is done by collecting only the hot fields into a new structure and rearranging the dimensions in the new array (of the new structure) to minimize stride width, e.g. a[x][y] to a[y][x]
Links in a linker mapfile that aligns text, data, and bss on 256 MB boundaries.
Links in a library of general purpose memory allocation routines which can be faster than those found in libc, at the expense of more virtual memory consumed.
Collect profile data for feedback-directed optimization. If an option directory is named, the feedback will be stored there.
When FDO is used, the training run gathers information regarding execution paths and data values. Hardware performance counters are not used. FDO improves existing optimizations but does not introduce new classes of optimization.
Use data collected for profile feedback. If an option directory is named, look for the feedback data there.
A convenience option, this switch selects several other options that are described in this file.
A convenience option, this switch selects the following switches that are described in this file:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Perform optimizations across all object files in the link step:
At -xipo=2, the compiler performs inter-procedural aliasing analysis as well as optimization of memory allocation and layout to improve cache performance.
Allows the compiler to perform type-based alias analysis at the specified alias level:
Adjust the compiler's assumptions about prefetch latency by the specified factor. Typically values in the range of 0.5 to 2.0 will be useful. A lower number might indicate that data will usually be cache resident; a higher number might indicate a relatively larger gap between the processor speed and the memory speed (compared to the assumptions built into the compiler).
Allocate routine local variables on the stack.
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
A convenience option, this switch selects several other options that are described in this file.
A convenience option, this switch selects the following switches that are described in this file:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Enables the use of the fused multiply-add instruction.
Set the preferred page size for running the program.
Enable unrolling loops n times where possible.
Adjust the compiler's assumptions about prefetch latency by the specified factor. Typically values in the range of 0.5 to 2.0 will be useful. A lower number might indicate that data will usually be cache resident; a higher number might indicate a relatively larger gap between the processor speed and the memory speed (compared to the assumptions built into the compiler).
Disable loop unroll and jam optimization in iropt
Specify optimization level n:
Links in a linker mapfile that enables the creation of a 'bss' segment, and aligns the segment at 4MB. This effectively provides an appropriate alignment for large page mapping of the heap.
Specify the -xjobs option to set how many processes the compiler creates to complete its work. Currently, -xjobs works only with the -xipo option. When you specify -xjobs=n, the interprocedural optimizer uses n as the maximum number of code generator instances it can invoke to compile different files.
Specify the -xjobs option to set how many processes the compiler creates to complete its work. Currently, -xjobs works only with the -xipo option. When you specify -xjobs=n, the interprocedural optimizer uses n as the maximum number of code generator instances it can invoke to compile different files.
Specify the -xjobs option to set how many processes the compiler creates to complete its work. Currently, -xjobs works only with the -xipo option. When you specify -xjobs=n, the interprocedural optimizer uses n as the maximum number of code generator instances it can invoke to compile different files.
Specify the -xjobs option to set how many processes the compiler creates to complete its work. Currently, -xjobs works only with the -xipo option. When you specify -xjobs=n, the interprocedural optimizer uses n as the maximum number of code generator instances it can invoke to compile different files.
Specify the -xjobs option to set how many processes the compiler creates to complete its work. Currently, -xjobs works only with the -xipo option. When you specify -xjobs=n, the interprocedural optimizer uses n as the maximum number of code generator instances it can invoke to compile different files.
Specify the -xjobs option to set how many processes the compiler creates to complete its work. Currently, -xjobs works only with the -xipo option. When you specify -xjobs=n, the interprocedural optimizer uses n as the maximum number of code generator instances it can invoke to compile different files.
Specify the -xjobs option to set how many processes the compiler creates to complete its work. Currently, -xjobs works only with the -xipo option. When you specify -xjobs=n, the interprocedural optimizer uses n as the maximum number of code generator instances it can invoke to compile different files.
Specify the -xjobs option to set how many processes the compiler creates to complete its work. Currently, -xjobs works only with the -xipo option. When you specify -xjobs=n, the interprocedural optimizer uses n as the maximum number of code generator instances it can invoke to compile different files.
This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.
Allows the compiler to assume that your code does not rely on setting of the errno variable.
Sets the maximum assumed data alignment:
Selects faster (but nonstandard) handling of floating point arithmetic exceptions and gradual underflow.
Controls simplifying assumptions for floating point arithmetic:
Evaluate float expressions as single precision.
Turns off all IEEE 754 trapping modes.
Allows the compiler to perform type-based alias analysis at the specified alias level:
Substitute intrinsic functions or inline system functions where profitable for performance.
Analyze loops for inter-iteration data dependencies, and do loop restructuring. Loop restructuring includes loop interchange, loop fusion, scalar replacement, and elimination of "dead" array assignments.
Use inline expansion for math library, libm.
Select the optimized math library.
Specify optimization level n:
Selects options for architecture, chip timing, and cache sizes. These can also be controlled separately, via -xarch, -xchip, and -xcache, respectively. A wide variety of targets can be selected, including ultra3, ultra3cu, ultra3i, ultra3iplus, ultra4, ultra4plus, ultraT1, ultraT2, sparc64vi. In each case, appropriate options are selected for architecture, chip timing, and cache size to match that target.
If -xtarget=native is selected, options that are appropriate for the system where the compile is being done.
The default is -xtarget=generic, which sets the parameters for the best performance over most 32-bit platform architectures.
On Solaris SPARC systems, the default pointer size with -xtarget=native is 32-bit.
Specifies which instructions can be used. Among the choices are:
xcache defines the cache properties for use by the optimizer. It can specify use of default assumptions ("generic"); use of whatever the compiler can assume about the current platform ("native"); or an explicit description of up to three levels of cache, using colon-separated specifiers of the form si/li/ai, where:
xchip determines timing properties that are assumed by the compiler. It does not limit which instructions are allowed (see xtarget for that). Among the choices are:
Assume data is naturally aligned.
Sets the IEEE 754 trapping mode to common exceptions (invalid, division by zero, and overflow).
Pad local variables, for better use of cache.
Allow the compiler to transform math library calls within loops into calls to the vector math library. Specifying
MTEXCLUSIVE
If set to "Y", additional memory allocation buckets will be created, so that threads will not need to share buckets
unless more than 2*NCPUS threads are created. This variable is used by mtmalloc.
OMP_NUM_THREADS
Sets the number of threads to use in OpenMP parallel regions.
SUNW_MP_PROCBIND
Binds threads in an OpenMP program to the virtual processors enumerated in the assignment. Can also be set to TRUE,
which casues threads to be bound in a round-robin fashion.
SUNW_MP_THR_IDLE
Specifies whether idle threads should SLEEP or SPIN.
STACKSIZE=<n>
Set the size of the stack (temporary storage area) for each slave thread of a multithreaded program.
ulimit -s <n>
Sets the stack size to n kbytes, or "unlimited" to allow the stack size to grow without limit.
Note that the "heap" and the "stack" share space; if your application allocates large amounts of memory on the heap,
then you may find that the stack limit should not be set to "unlimited". A commonly used setting for SPEC CPU2006 purposes
is a stack size of 128MB (131072K).
Flag description origin markings:
|
Indicates that the flag description came from the user flags file. |
![[suite]](http://www.spec.org/auto/cpu2006/flags/suite.png) |
Indicates that the flag description came from the suite-wide flags file. |
![[benchmark]](http://www.spec.org/auto/cpu2006/flags/benchmark.png) |
Indicates that the flag description came from a per-benchmark flags file. |
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2006-2014 Standard Performance Evaluation Corporation
Tested with SPEC CPU2006 v1.2.
Report generated on Thu Jul 24 23:22:18 2014 by SPEC CPU2006 flags formatter v6906.