SPEC(R) CINT2006 Summary Cisco Systems Cisco UCS C480 M5 (Intel Xeon Platinum 8180, 2.50GHz) Sun Jun 25 14:06:42 2017 CPU2006 License: 9019 Test date: Jun-2017 Test sponsor: Cisco Systems Hardware availability: Aug-2017 Tested by: Cisco Systems Software availability: Sep-2017 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 224 505 4340 * 400.perlbench 224 505 4330 S 400.perlbench 224 505 4340 S 401.bzip2 224 863 2500 S 401.bzip2 224 863 2510 S 401.bzip2 224 863 2500 * 403.gcc 224 495 3640 S 403.gcc 224 491 3670 S 403.gcc 224 492 3670 * 429.mcf 224 309 6600 * 429.mcf 224 309 6610 S 429.mcf 224 310 6590 S 445.gobmk 224 668 3520 S 445.gobmk 224 667 3520 S 445.gobmk 224 667 3520 * 456.hmmer 224 286 7310 S 456.hmmer 224 285 7340 S 456.hmmer 224 285 7320 * 458.sjeng 224 718 3780 S 458.sjeng 224 718 3770 S 458.sjeng 224 718 3780 * 462.libquantum 224 46.0 101000 * 462.libquantum 224 46.1 101000 S 462.libquantum 224 45.9 101000 S 464.h264ref 224 772 6420 * 464.h264ref 224 775 6390 S 464.h264ref 224 772 6420 S 471.omnetpp 224 583 2400 S 471.omnetpp 224 583 2400 * 471.omnetpp 224 583 2400 S 473.astar 224 557 2820 S 473.astar 224 558 2820 S 473.astar 224 557 2820 * 483.xalancbmk 224 295 5230 S 483.xalancbmk 224 295 5250 * 483.xalancbmk 224 293 5270 S ============================================================================== 400.perlbench 224 505 4340 * 401.bzip2 224 863 2500 * 403.gcc 224 492 3670 * 429.mcf 224 309 6600 * 445.gobmk 224 667 3520 * 456.hmmer 224 285 7320 * 458.sjeng 224 718 3780 * 462.libquantum 224 46.0 101000 * 464.h264ref 224 772 6420 * 471.omnetpp 224 583 2400 * 473.astar 224 557 2820 * 483.xalancbmk 224 295 5250 * SPECint(R)_rate_base2006 5380 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon Platinum 8180 CPU Characteristics: Intel Turbo Boost Technology up to 3.80 GHz CPU MHz: 2500 FPU: Integrated CPU(s) enabled: 112 cores, 4 chips, 28 cores/chip, 2 threads/core CPU(s) orderable: 2,4 chips Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 1 MB I+D on chip per core L3 Cache: 38.5 MB I+D on chip per chip Other Cache: None Memory: 768 GB (48 x 16 GB 2Rx4 PC4-2666V-R) Disk Subsystem: 1 x 400 GB SSD SAS Other Hardware: None SOFTWARE -------- Operating System: SUSE Linux Enterprise Server 12 SP2 (x86_64) 4.4.21-69-default Compiler: C/C++: Version 18.0.0.082 of Intel C/C++ Beta Compiler for Linux Auto Parallel: No File System: xfs System State: Run level 3 (multi-user) Base Pointers: 32-bit Peak Pointers: 32/64-bit Other Software: Microquill SmartHeap V10.2 Submit Notes ------------ The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" Platform Notes -------------- Intel HyperThreading Technology set to Enabled CPU performance set to Enterprise Power Performance Tuning set to OS SNC set to Enabled IMC Interleaving set to 1-way Interleave Patrol Scrub set to Disabled Sysinfo program /home/cpu2006-1.2/config/sysinfo.rev6993 Revision 6993 of 2015-11-06 (b5e8d4b4eb51ed28d7f98696cbe290c1) running on linux-k2f8 Sun Jun 25 14:06:43 2017 This section contains SUT (System Under Test) info as seen by some common utilities. To remove or add to this section, see: http://www.spec.org/cpu2006/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Platinum 8180 CPU @ 2.50GHz 4 "physical id"s (chips) 224 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 28 siblings : 56 physical 0: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 16 17 18 19 20 21 22 24 25 26 27 28 29 30 physical 1: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 16 17 18 19 20 21 22 24 25 26 27 28 29 30 physical 2: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 16 17 18 19 20 21 22 24 25 26 27 28 29 30 physical 3: cores 0 1 2 3 4 5 6 8 9 10 11 12 13 14 16 17 18 19 20 21 22 24 25 26 27 28 29 30 cache size : 39424 KB From /proc/meminfo MemTotal: 790980256 kB HugePages_Total: 0 Hugepagesize: 2048 kB /usr/bin/lsb_release -d SUSE Linux Enterprise Server 12 SP2 From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 2 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12-SP2" VERSION_ID="12.2" PRETTY_NAME="SUSE Linux Enterprise Server 12 SP2" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12:sp2" uname -a: Linux linux-k2f8 4.4.21-69-default #1 SMP Tue Oct 25 10:58:20 UTC 2016 (9464f67) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Jun 24 21:00 SPEC is set to: /home/cpu2006-1.2 Filesystem Type Size Used Avail Use% Mounted on /dev/sda3 xfs 404G 33G 372G 8% /home Additional information from dmidecode: Warning: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Cisco Systems, Inc. C480M5.3.1.0.272.0613172154 06/13/2017 Memory: 48x 0xCE00 M393A2G40EB2-CTD 16 GB 2 rank 2666 MHz (End of data from sysinfo program) General Notes ------------- Environment variables set by runspec before the start of the run: LD_LIBRARY_PATH = "/opt/intel/compilers_and_libraries_2018.0.082/linux/compiler/lib/ia32:/opt/intel/compilers_and_libraries_2018.0.082/linux/compiler/lib/intel64:/home/cpu2006-1.2/sh10.2" Binaries compiled on a system with 1x Intel Core i7-4790 CPU + 32GB RAM memory using Redhat Enterprise Linux 7.2 Transparent Huge Pages enabled with: echo always > /sys/kernel/mm/transparent_hugepage/enabled Filesystem page cache cleared with: shell invocation of 'sync; echo 3 > /proc/sys/vm/drop_caches' prior to run runspec command invoked through numactl i.e.: numactl --interleave=all runspec Base Compiler Invocation ------------------------ C benchmarks: icc -m32 -L/opt/intel/compilers_and_libraries_2018.0.082/linux/lib/ia32 C++ benchmarks: icpc -m32 -L/opt/intel/compilers_and_libraries_2018.0.082/linux/lib/ia32 Base Portability Flags ---------------------- 400.perlbench: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX_IA32 401.bzip2: -D_FILE_OFFSET_BITS=64 403.gcc: -D_FILE_OFFSET_BITS=64 429.mcf: -D_FILE_OFFSET_BITS=64 445.gobmk: -D_FILE_OFFSET_BITS=64 456.hmmer: -D_FILE_OFFSET_BITS=64 458.sjeng: -D_FILE_OFFSET_BITS=64 462.libquantum: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX 464.h264ref: -D_FILE_OFFSET_BITS=64 471.omnetpp: -D_FILE_OFFSET_BITS=64 473.astar: -D_FILE_OFFSET_BITS=64 483.xalancbmk: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -xHOST -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 C++ benchmarks: -xHOST -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 -Wl,-z,muldefs -L/home/cpu2006-1.2/sh10.2 -lsmartheap Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic17.0-official-linux64-revF.html http://www.spec.org/cpu2006/flags/Cisco-Platform-Settings-V1.2-revG.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2006/flags/Intel-ic17.0-official-linux64-revF.xml http://www.spec.org/cpu2006/flags/Cisco-Platform-Settings-V1.2-revG.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2017 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.2. Report generated on Thu Jul 13 12:50:41 2017 by CPU2006 ASCII formatter v6932. Originally published on 13 July 2017.