SPEC(R) CINT2006 Summary Cisco Systems Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz) Mon Jan 4 15:16:44 2010 CPU2006 License: 9019 Test date: Jan-2010 Test sponsor: Cisco Systems Hardware availability: Aug-2017 Tested by: Cisco Systems Software availability: Apr-2017 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 48 545 861 S 400.perlbench 48 548 856 S 400.perlbench 48 545 860 * 401.bzip2 48 907 511 S 401.bzip2 48 940 493 S 401.bzip2 48 923 502 * 403.gcc 48 459 843 * 403.gcc 48 458 844 S 403.gcc 48 462 837 S 429.mcf 48 267 1640 S 429.mcf 48 270 1620 S 429.mcf 48 269 1630 * 445.gobmk 48 697 723 * 445.gobmk 48 697 723 S 445.gobmk 48 697 723 S 456.hmmer 48 263 1710 * 456.hmmer 48 262 1710 S 456.hmmer 48 263 1710 S 458.sjeng 48 743 782 * 458.sjeng 48 743 781 S 458.sjeng 48 743 782 S 462.libquantum 48 47.1 21100 * 462.libquantum 48 46.9 21200 S 462.libquantum 48 47.2 21100 S 464.h264ref 48 822 1290 * 464.h264ref 48 834 1270 S 464.h264ref 48 795 1340 S 471.omnetpp 48 487 616 S 471.omnetpp 48 487 616 * 471.omnetpp 48 487 616 S 473.astar 48 509 662 S 473.astar 48 506 665 S 473.astar 48 507 665 * 483.xalancbmk 48 228 1450 S 483.xalancbmk 48 227 1460 * 483.xalancbmk 48 227 1460 S ============================================================================== 400.perlbench 48 545 860 * 401.bzip2 48 923 502 * 403.gcc 48 459 843 * 429.mcf 48 269 1630 * 445.gobmk 48 697 723 * 456.hmmer 48 263 1710 * 458.sjeng 48 743 782 * 462.libquantum 48 47.1 21100 * 464.h264ref 48 822 1290 * 471.omnetpp 48 487 616 * 473.astar 48 507 665 * 483.xalancbmk 48 227 1460 * SPECint(R)_rate_base2006 1200 SPECint_rate2006 Not Run HARDWARE -------- CPU Name: Intel Xeon Gold 5118 CPU Characteristics: Intel Turbo Boost Technology up to 3.20 GHz CPU MHz: 2300 FPU: Integrated CPU(s) enabled: 24 cores, 2 chips, 12 cores/chip, 2 threads/core CPU(s) orderable: 1,2 chips Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 1 MB I+D on chip per core L3 Cache: 16.5 MB I+D on chip per chip Other Cache: None Memory: 384 GB (24 x 16 GB 2Rx4 PC4-2666V-R, running at 2400 MHz) Disk Subsystem: 1 x 240 GB M.2 SATA SSD Other Hardware: None SOFTWARE -------- Operating System: SUSE Linux Enterprise Server 12 SP2 (x86_64) 4.4.21-69-default Compiler: C/C++: Version 18.0.0.128 of Intel C/C++ Compiler for Linux; Fortran: Version 18.0.0.128 of Intel Fortran Auto Parallel: No File System: xfs System State: Run level 3 (multi-user) Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: Microquill SmartHeap V10.2 Submit Notes ------------ The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" Platform Notes -------------- BIOS Settings: Intel HyperThreading Technology set to Enabled CPU performance set to Enterprise Power Performance Tuning set to OS SNC set to Enabled IMC Interleaving set to 1-way Interleave Patrol Scrub set to Disabled Sysinfo program /home/cpu2006-ic18/config/sysinfo.rev6993 Revision 6993 of 2015-11-06 (b5e8d4b4eb51ed28d7f98696cbe290c1) running on linux-mys2 Mon Jan 4 12:16:45 2010 This section contains SUT (System Under Test) info as seen by some common utilities. To remove or add to this section, see: http://www.spec.org/cpu2006/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Gold 5118 CPU @ 2.30GHz 2 "physical id"s (chips) 48 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 12 siblings : 24 physical 0: cores 0 1 2 3 4 5 8 9 10 11 12 13 physical 1: cores 0 1 2 3 4 5 8 9 10 11 12 13 cache size : 16896 KB From /proc/meminfo MemTotal: 394832004 kB HugePages_Total: 0 Hugepagesize: 2048 kB /usr/bin/lsb_release -d SUSE Linux Enterprise Server 12 SP2 From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 2 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12-SP2" VERSION_ID="12.2" PRETTY_NAME="SUSE Linux Enterprise Server 12 SP2" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12:sp2" uname -a: Linux linux-mys2 4.4.21-69-default #1 SMP Tue Oct 25 10:58:20 UTC 2016 (9464f67) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Jan 1 02:31 SPEC is set to: /home/cpu2006-ic18 Filesystem Type Size Used Avail Use% Mounted on /dev/sda3 xfs 182G 21G 162G 12% /home Additional information from dmidecode: Warning: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Cisco Systems, Inc. B200M5.3.2.1d.5.0727171353 07/27/2017 Memory: 24x 0xCE00 M393A2G40EB2-CTD 16 GB 2 rank 2666 MHz, configured at 2400 MHz (End of data from sysinfo program) General Notes ------------- Environment variables set by runspec before the start of the run: LD_LIBRARY_PATH = "/opt/intel/compilers_and_libraries_2018.0.128/linux/compiler/lib/ia32:/opt/intel/compilers_and_libraries_2018.0.128/linux/compiler/lib/intel64:/home/cpu2006-ic18/sh10.2" Binaries compiled on a system with 1x Intel Core i7-4790 CPU + 32GB RAM memory using Redhat Enterprise Linux 7.2 Transparent Huge Pages enabled with: echo always > /sys/kernel/mm/transparent_hugepage/enabled Filesystem page cache cleared with: shell invocation of 'sync; echo 3 > /proc/sys/vm/drop_caches' prior to run runspec command invoked through numactl i.e.: numactl --interleave=all runspec Base Compiler Invocation ------------------------ C benchmarks: icc -m32 -L/opt/intel/compilers_and_libraries_2018.0.128/linux/compiler/lib/ia32 C++ benchmarks: icpc -m32 -L/opt/intel/compilers_and_libraries_2018.0.128/linux/compiler/lib/ia32 Base Portability Flags ---------------------- 400.perlbench: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX_IA32 401.bzip2: -D_FILE_OFFSET_BITS=64 403.gcc: -D_FILE_OFFSET_BITS=64 429.mcf: -D_FILE_OFFSET_BITS=64 445.gobmk: -D_FILE_OFFSET_BITS=64 456.hmmer: -D_FILE_OFFSET_BITS=64 458.sjeng: -D_FILE_OFFSET_BITS=64 462.libquantum: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX 464.h264ref: -D_FILE_OFFSET_BITS=64 471.omnetpp: -D_FILE_OFFSET_BITS=64 473.astar: -D_FILE_OFFSET_BITS=64 483.xalancbmk: -D_FILE_OFFSET_BITS=64 -DSPEC_CPU_LINUX Base Optimization Flags ----------------------- C benchmarks: -xHOST -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 C++ benchmarks: -xHOST -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 -Wl,-z,muldefs -L/home/cpu2006-1.2/sh10.2 -lsmartheap Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic17.0-official-linux64-revF.html http://www.spec.org/cpu2006/flags/Cisco-Platform-Settings-V1.2-revH.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2006/flags/Intel-ic17.0-official-linux64-revF.xml http://www.spec.org/cpu2006/flags/Cisco-Platform-Settings-V1.2-revH.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2018 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.2. Report generated on Fri Apr 20 18:45:12 2018 by CPU2006 ASCII formatter v6932. Originally published on 12 October 2017.