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<!DOCTYPE flagsdescription SYSTEM "http://www.spec.org/dtd/cpuflags2.dtd">

<flagsdescription>

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<filename>BullSequanaSH-Flags-V1.0</filename>

<title>SPEC CPU2017 Platform Settings for Intel-based systems</title>

<os_tuning>	 
<![CDATA[
<dl>  
<dt><b>ulimit -s &lt;n&gt; </b></dt>
   <dd>
        Sets the stack size to <b>n</b> kbytes, or <b>unlimited</b> to allow the stack size 
         to grow without limit.
		
   </dd>    

<dt><b>cpupower:</b></dt> 
<dd>
	The OS 'cpupower' utility is used to change CPU power governors settings. Available settings are: <ul> 
	<li>performance: Run the CPU at the maximum frequency.</li> 
	<li>powersave(default): Run the CPU at the minimum frequency.</li> </ul> 
</dd> 

<dt><b>tuned-adm:</b></dt> 
<dd> 
	The 'tuned' provides a number of predefined profiles for typical use cases. The 'tuned-adm' command is used to change settings of the tuned daemon. The tuned-adm command can query current settings, list available profiles, recommend a tuning profile for the system, change profiles directly, or turn off tuning. Available profiles are: <ul> 
	<li>accelerator-performance: Throughput-performance based tuning with disabled higher latency STOP states. </li>
	<li>balanced: General non-specialized tuned profile.</li> <li>desktop: Optimize for the desktop use-case.</li> 
	<li>hpc-compute: Optimize for HPC compute workloads.</li> <li>intel-sst: Configure for Intel Speed Select Base Frequency.</li>
	<li>latency-performance: Optimize for deterministic performance at the cost of increased power consumption.</li> 
	<li>network-latency: Optimize for deterministic performance at the cost of increased power consumption, focused on low latency network performance.</li> 
	<li>network-throughput: Optimize for streaming network throughput, generally only necessary on older CPUs or 40G+ networks.</li>
	<li>optimize-serial-console: Optimize for serial console use.</li> 
	<li>powersave: Optimize for low power consumption.</li> 
	<li>throughput-performance(default): Broadly applicable tuning that provides excellent performance across a variety of common server workloads.</li> 
	<li>virtual-guest: Optimize for running inside a virtual guest.</li> 
	<li>virtual-host: Optimize for running KVM guests.</li> </ul> 
</dd> 

<dt><b>transparent_hugepages:</b></dt>
	<dd>
		Processes are allowed to use hugepages by writing "always" to the system file/sys/kernel/mm/transparent_hugepage.
		Possible options are:
		<ul>
		<li>always:
means that an application requesting THP will stall on allocation failure and directly reclaim pages and compact memory in an effort to allocate a THP immediately. This may be desirable for virtual machines that benefit heavily from THP use and are willing to delay the VM start to utilise them.</li>

		<li>madvise: 
will enter direct reclaim like always but only for regions that are have used madvise(MADV_HUGEPAGE). This is the default behaviour.</li>

		<li>never:
should be self-explanatory.</li>
		</ul>
	</dd>

<dt><b>numactl --interleave=all "runspec command"</b></dt> 
   <dd>
   Launching a process with numactl --interleave=all sets the memory interleave policy so that memory will be allocated using 
   round robin on nodes. When memory cannot be allocated on the current interleave target fall back to other nodes. 
   </dd>

</dl>

]]>
</os_tuning>

<firmware>

<![CDATA[
<dl>
<dt><b>Patrol Scrub</b></dt> 
<dd>
      This BIOS option allows to configure the periodicity of memory scrubbing.<ul>
      <li>Setting this BIOS option to Disable, no systematic periodic scrubbing is done</li>
      <li>Setting this BIOS option to an integer from 1 to 24 ensures all the memory is scanned in that number of hours</li>
	  </ul>
</dd>

<dt><b>SNC</b></dt> 
 <dd>
  Sub NUMA Clustering (SNC) is a feature for breaking up the LLC into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system.
  It improves average latency to the LLC and is an important pre-requisite to enabling KTI prefetch and is a replacement for the Cluster-on-Die feature found in previous processors.
  <ul>
  <li>Enable SNC4 (4-clusters): supports 2-way clustering. Utilizes LLC capacity efficiently and reduces latency due to core/IMC proximity. This may provide performance improvement on NUMA-aware operating systems.</li>

  <li>Enable SNC2 (2-clusters): supports 4-way clustering. Utilizes LLC capacity more efficiently and reduces latency due to core/IMC proximity. This may provide performance improvement on NUMA-aware operating systems.</li>

  <li>Disabled: supports 1-cluster and 2-way IMC interleave, the LLC is treated as one cluster.</li>
  </ul>
 </dd>

<dt><b>Power Performance Tuning</b></dt>
  <dd>
  Define who is responsible for managing Energy / Performance Balance
  <ul>
  <li>OS Controls EPB: Energy/ performance balance is managed by the operating system</li>
  <li>BIOS Controls EPB: Energy/ performance balance is managed by the BIOS</li>
  <li>PECI Controls EPB: Energy/ performance balance is managed by Intel's Platform Environment Control Interface</li>
  </ul>
</dd>
  
<dt><b>Energy Perf Bias CFG mode</b></dt> 
 <dd>
  This BIOS option allows for processor performance and power optmization. Available settings are:
  <ul>
  <li>Performance0: High performance with less need for power saving.</li>
  <li>Balanced Performance0 (Default Setting): Provides optimal performance efficiency.</li>
  <li>Balanced Power0: Provides optimal power efficiency.</li>
  <li>Power0: High power saving with less need for performance.</li>
  </ul>
</dd>

<dt><b>DCU Streamer Prefetcher</b></dt>
  <dd>
    <p>DCU (Level 1 Data Cache) streamer prefetcher is an L1 data cache prefetcher. Lightly threaded applications and some benchmarks can benefit from having the DCU streamer prefetcher enabled. </p>
	<p>Default setting is Enable.</p>
  </dd>

<dt><b>Last Level Cache (LLC)Prefetch</b></dt>
  <dd>
    <p>This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit (DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.</p>
    <p>Values for this BIOS option can be:</p>
	<ul>
    <li>Disabled: Disables the LLC prefetcher. The other core prefetchers are unaffected.</li>
    <li>Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.</li>
	</ul>
  </dd>

<dt><b>LLC dead line alloc:</b></dt> 
 <dd>
  In the processor non-inclusive cache scheme, MLC evictions are filled into the LLC. When lines are evicted from the MLC, the core can flag them as “dead” (i.e., not likely to be read again). The LLC has the option to drop dead lines and not fill them in the LLC. This can help save space in the LLC and prevent the LLC from evicting useful data.  Available settings are:
  <ul>
	  <li>Disabled: Disabling this option can save space in the LLC by never moving MLC dead lines into the LLC.</li>
	  <li>Enabled(default): Opportunistically move MLC dead lines into the LLC, if space is available.</li>
  </ul>
</dd>

<dt>Package C State</dt>
<dd>
	This option allows the user to select the highest sleep state authororized on the system.
<ul>
	<li>C0/C1 state: the CPUs are always fully turned on</li>
		<li>C2: Core and bus clocks are off. The processor maintains all software-visible state, but can take longer to wake up.</li>
		<li>C6: authorizes very deep sleep, making the CPU take a long time to be operational after each sleep</li>
</ul></dd>

<dt><b>Link disable</b></dt>
  <dd>
    <p>Four UPI links are present between the two sockets of the BullSequana SH20. Each UPI link is power consuming
	and is not necessary for a well localized benchmark as specCPU</p>
	<p>Disabling three out of four links allows power saving at UPI level and increased frequency of the core part
	of the CPU package</p>
	
	<p>The BIOS setting "Link Disable" is present for all 4 UPI ports of the 2 CPU packages.</p>
	<p>This setting can be found in Advanced settings / Socket configuration / Uncore configuration / Uncore Per Socket Configuration / CPU Nb / CPU Nb UPI Port 0-3</p>	
    <p>Values for this BIOS option can be:</p>
	<ul>
    <li>No (default): The UPI port is enabled</li>
    <li>Yes: The UPI port is disabled</li>
	</ul>
	<p>To keep only one link, all settings are set to Yes except CPU 0 UPI Port 0  and CPU 1 UPI Port 1</p>
  </dd>
  
<dt><b>Enable dIout tuning</b></dt>
<dd>
		Performance tuning option:
		<ul>
			<li>Enabled: system runs with optimized performances</li>
			<li>Disabled: these optmizations will not be activated</li>
		</ul>
</dd>


<dt><b>FansFullSpeed</b></dt>
  <dd>
	By default, the fan speed is regulated to keep the processor temperature just below the maximum
	To lower the processor temperature, fans are set to the maximum speed using a redfish command on the BMC.
	
	<p>curl -k -u "bmcLogin":"passwd" -H "Content-Type: application/json" -d '{"Oem":{"Eviden_com":{"FansFullSpeed": true}}}' -X PATCH https://"bmc ip address"/redfish/v1/Chassis/Module0/Thermal</p>
  </dd>
  </dl>
]]>

  </firmware>

</flagsdescription>
