SPEC CPU20017 Platform Settings for Epsylon systems based on Intel Solutions

Firmware / BIOS / Microcode Settings

Intel(R) Hyper-Threading Tech:
Intel(R) Hyper-Threading Technology allows multithreaded software applications to execute threads in parallel within each processor.
The options are [Disabled] and [Enabled].
Users should set this option as [Enabled] for performing CPU2017 INT/FP Rate benchmark.
Users should set this option as [Disabled] for performing CPU2017 INT/FP Speed benchmark.
CPU Power and Performance Policy:
Allows the user to set an overall power and performance policy for the system.
[Balanced Performance] - Weights optimization toward performance, while conserving energy.
[Performance] - Optimization is strongly toward pweformance, even at the expense of energy efficiency.
[Balanced Power] - Weights optimization toward energy conservation, with good performance.
[Power] - Optimization is stronglytoward energy efficiency, even at the expense of performance.
Users should set this option as [Performance] for performing application benchmarking.
Intel(R) Turbo Boost Technology:
The options are [Disabled] and [Enabled].
This option Allows the processor to automatically increrase its frequency if it is running below power, temperature, and current specifications.
Users should set this option as [Enabled] for performing application benchmarking.
C1E:
The options are [Disabled] and [Enabled].
When enabled, C1E halt state invoked by the operating system's idle process turns down the entire CPU's clock frequency and voltage and cut a CPU's power consumption and heat production.
Users should set this option as [Disabled] for performing application benchmarking.
Processor C6:
The options are [Disabled] and [Enabled].
Enabling this option allows the processor to send the C6 report to the Operating system.
Users should set this option as [Disabled] for performing application benchmarking.
IMC Interleaving:
This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs).
The options are [Auto], [1-way Interleave] and [2-way Interleave].
There are two Integrated Memory Controllers in Skylake CPUs.
If IMC Interleaving is set to 2-way, addresses will be interleaved between the two IMCs. 
If IMC Interleaving is set to 1-way, there will be no interleaving.  
If Sub_NUMA Cluster is disabled, IMC Interleaving should be set to 2-way.  
If Sub_NUMA Cluster is enabled, IMC Interleaving should be set to 1-way. 
Sub_NUMA Cluster:
This BIOS option provides similar localization benefits as Cluster-On-Die (COD), without some of COD downsides. 
Sub_NUMA Cluster breaks up the LLC into two disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. 
Sub_NUMA Cluster improves average latency to the LLC (last level cache) and memory. 
For a multi-socketed system, all clusters are mapped to unique NUMA domains. 
IMC Interleaving must be set to the correct value to correspond with Sub_NUMA Cluster enable/disable. 
The options are [Disabled] and [Enabled].
Set FAN Profile:
[Performance] - Fan control provides primary system cooling before attempting to throttle memory.
[Acoustic] - The system will favor using throttling of memory over boosting fans to cool the system if thermal thresholds are met.
Users should set this option as [Performance] for performing application benchmarking.
Patrol Scrub:
The options are [Disabled] and [Enabled].
When enabled, performs periodic checks on memory cells and proactively walks through populated memory space, to seek and correct soft ECC errors.
Users should set this option as [Disabled] for performing application benchmarking.