GIGA-BYTE-Platform-SPECcpu2017-Flags-V1.0-Intel-Purley.xml SPEC CPU2017 Platform Settings for GIGA-BYTE Intel Purley platform
Power Policy Quick Settings

This BIOS option controls the performance or power save setting, user can use this item to change it. Best performance can maximize the performance of the server. Energy efficiency can maximize the power efficiency of the server.

Values for this BIOS setting can be:

Standard: BIOS default setting.

Best Performance: Maximize the performance of the server.

Energy Efficiency: Maximize the power efficiency of the server.

SNC(Sub-NUMA Clustering)

SNC breaks up the last level cache (LLC) into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. SNC improves average latency to the LLC and memory. SNC is a replacement for the cluster on die (COD) feature found in previous processor families. For a multi-socketed system, all SNC clusters are mapped to unique NUMA (Non Uniform Memory Access) domains.

SNC AUTO supports 1-cluster or 2-clusters depending on IMC interleave. SNC and IMC interleave both AUTO will support 1-cluster 2-way IMC interleave.

SNC Enable supports Full SNC (2 clusters) and 1-way IMC interleave.

SNC disable supports 1-cluster and 2-way IMC interleave, the LLC is treated as one cluster.

Stale AtoS (Directory AtoS)

This BIOS switch allows 2 options: "Enabled" and "Disabled". The default is "Disabled".

The in-memory directory has three states: I, A, and S. I (invalid) state means the data is clean and does not exist in any other socket's cache. A (snoopAll) state means the data may exist in another socket in exclusive or modified state. S (Shared) state means the data is clean and may be shared across one or more socket's caches.

When doing a read to memory, if the directory line is in the A state we must snoop all the other sockets because another socket may have the line in modified state. If this is the case, the snoop will return the modified data. However, it may be the case that a line is read in A state and all the snoops come back a miss. This can happen if another socket read the line earlier and then silently dropped it from its cache without modifying it.

If Stale AtoS feature is enabled, in the situation where a line in A state returns only snoop misses, the line will transition to S state. That way, subsequent reads to the line will encounter it in S state and not have to snoop, saving latency and snoop bandwidth. Stale AtoS may be beneficial in a workload where there are many cross-socket reads.

LLC dead line alloc

In some Intel CPU caching schemes, mid-level cache (MLC) evictions are filled into the last level cache (LLC). If a line is evicted from the MLC to the LLC, the core can flag the evicted MLC lines as "dead.” This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if the option is disabled.

Values for this BIOS option can be:

Disabled: Disabling this option can save space in the LLC by never filling MLC dead lines into the LLC.

Enabled: Opportunistically fill MLC dead lines in LLC, if space is available.

IMC Interleaving

This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs). There are two IMCs per socket in Skylake Server. If IMC Interleaving is set to 2-way, addresses will be interleaved between the two IMCs. If IMC Interleaving is set to 1-way, there will be no interleaving. If SNC is disabled, IMC Interleaving should be set to 2-way. If SNC is enabled, IMC Interleaving should be set to 1-way. Default setting is "Auto".

Patrol Scrub

This BIOS option enables or disables the so-called memory scrubbing, which cyclically accesses the main memory of the system in the background regardless of the operating system in order to detect and correct memory errors in a preventive way. The time of this memory test cannot be influenced and can under certain circumstances result in losses in performance. The disabling of the Patrol Scrub option increases the probability of discovering memory errors in case of active accesses by the operating system. Until these errors are correctable, the ECC technology of the memory modules ensures that the system continues to run in a stable way. However, too many correctable memory errors increase the risk of discovering non-correctable errors, which then result in a system standstill.

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