CPU2017 Flag Description
Dell Inc. PowerEdge R930 (Intel Xeon E7-8890 v4, 2.20 GHz)

Copyright © 2016 Intel Corporation. All Rights Reserved.


Base Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Base Portability Flags

503.bwaves_r

507.cactuBSSN_r

508.namd_r

510.parest_r

511.povray_r

519.lbm_r

521.wrf_r

526.blender_r

527.cam4_r

538.imagick_r

544.nab_r

549.fotonik3d_r

554.roms_r


Base Optimization Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.


Commands and Options Used to Submit Benchmark Runs

submit= MYMASK=`printf '0x%x' $((1<<$SPECCOPYNUM))`; /usr/bin/taskset $MYMASK $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command, using taskset, is used for Linux64 systems without numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:
submit= numactl --localalloc --physcpubind=$SPECCOPYNUM $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command is used for Linux64 systems with support for numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:

Shell, Environment, and Other Software Settings

numactl --interleave=all "runspec command"
Launching a process with numactl --interleave=all sets the memory interleave policy so that memory will be allocated using round robin on nodes. When memory cannot be allocated on the current interleave target fall back to other nodes.
KMP_STACKSIZE
Specify stack size to be allocated for each thread.
KMP_AFFINITY
Syntax: KMP_AFFINITY=[<modifier>,...]<type>[,<permute>][,<offset>]
The value for the environment variable KMP_AFFINITY affects how the threads from an auto-parallelized program are scheduled across processors.
It applies to binaries built with -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows).
modifier:
    granularity=fine Causes each OpenMP thread to be bound to a single thread context.
type:
    compact Specifying compact assigns the OpenMP thread <n>+1 to a free thread context as close as possible to the thread context where the <n> OpenMP thread was placed.
    scatter Specifying scatter distributes the threads as evenly as possible across the entire system.
permute: The permute specifier is an integer value controls which levels are most significant when sorting the machine topology map. A value for permute forces the mappings to make the specified number of most significant levels of the sort the least significant, and it inverts the order of significance.
offset: The offset specifier indicates the starting position for thread assignment.

Please see the Thread Affinity Interface article in the Intel Composer XE Documentation for more details.

Example: KMP_AFFINITY=granularity=fine,scatter
Specifying granularity=fine selects the finest granularity level and causes each OpenMP or auto-par thread to be bound to a single thread context.
This ensures that there is only one thread per core on cores supporting HyperThreading Technology
Specifying scatter distributes the threads as evenly as possible across the entire system.
Hence a combination of these two options, will spread the threads evenly across sockets, with one thread per physical core.

Example: KMP_AFFINITY=compact,1,0
Specifying compact will assign the n+1 thread to a free thread context as close as possible to thread n.
A default granularity=core is implied if no granularity is explicitly specified.
Specifying 1,0 sets permute and offset values of the thread assignment.
With a permute value of 1, thread n+1 is assigned to a consecutive core. With an offset of 0, the process's first thread 0 will be assigned to thread 0.
The same behavior is exhibited in a multisocket system.
OMP_NUM_THREADS
Sets the maximum number of threads to use for OpenMP* parallel regions if no other value is specified in the application. This environment variable applies to both -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores: export OMP_NUM_THREADS=8
Set stack size to unlimited
The command "ulimit -s unlimited" is used to set the stack size limit to unlimited.
Free the file system page cache
The command "echo 1> /proc/sys/vm/drop_caches" is used to free up the filesystem page cache.

Red Hat Specific features

Transparent Huge Pages
On RedHat EL 6 and later, Transparent Hugepages increase the memory page size from 4 kilobytes to 2 megabytes. Transparent Hugepages provide significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead.
Hugepages are used by default unless the /sys/kernel/mm/redhat_transparent_hugepage/enabled field is changed from its RedHat EL6 default of 'always'.

Firmware / BIOS / Microcode Settings

Hardware Prefetcher:

This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Adjacent Cache Line Prefetch:

This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within a 128-byte sector that contains the data needed due to a cache line miss. In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

High Bandwidth:

Enabling this option allows the chipset to defer memory transactions and process them out of order for optimal performance.

Data Reuse:

Enabling this BIOS option reduces the frequency of L3 cache updates from L1. This may improve performance by reducing the internal bandwidth consumed by constantly updating L1 cache lines in L3. Since this results in more fetches to main memory, setting this option to Disabled may improve performance in some cases. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Logical Processor:

This BIOS setting enables/disables Intel's Hyper-Threading (HT) Technology. With HT Technology, the operating system can execute two threads in parallel within each processor core.

Execute disable:

This is a security feature designed to prevent certain types of buffer overflow attacks by enforcing specific areas of memory that applications can execute code. In general, it is best to leave this option Enabled for the security benefits, as no real performance advantage has been detected by disabling this feature in BIOS

Virtualization technology:

When this option is enabled, the BIOS will enable processor Virtualization features and provide the virtualization support to the OS through the DMAR table. In general, only virtualized environments such as VMware ® ESX™, Microsoft Hyper-V ® , Red Hat ® KVM, and other virtualized operating systems will take advantage of these features. Disabling this feature is not known to significantly alter the performance or power characteristics of the system, so leaving this option Enabled is advised for most cases.

Node Interleaving:

This BIOS option allows the enabling/disabling of memory interleaving across CPU nodes. When disabled, each CPU chip can only access memory within its own node.

CPU Power Management:

This BIOS setting allows configuration of various demand-based switching schemes. Maximum Performance maintains full voltage to processor internal components, even during periods of inactivity, eliminating the performance penalty associated with the phase transitions between high and low load.

Memory Frequency:

This BIOS setting allows the memory to be clocked to the highest supported frequency.

Turbo Boost:

Intel Turbo Boost Technology is a processor feature which allows the processor to transition to a higher frequency than the processor's rate speed if the processor has available power headroom and is within temperature specifications. Disabling this feature will reduce power usage but will reduce the system's maximum achievable performance under some workloads.

C States:

Enabling the CPU States causes the CPU to enter a low-power mode when the CPU is idle.

System Profile:

This BIOS option sets the performance and power management aggressiveness for the system. It is a collection of selections including a custom selection designed to allow customers to choose the ideal operating profile for their server system environment. It includes settings like CPU Power Management, Memory Frequency, Turbo Boost, C1E and C States.

Memory Patrol Scrub:

Memory Patrol Scrub Patrol Scrubbing is a custom System Profile option feature that scans the memory for bit errors and corrects them whenever possible. When set to Disabled, no patrol scrubbing will occur. When set to Standard Mode, the entire memory array will be scrubbed once in a 24 hour period. When set to Extended Mode, the entire memory array will be scrubbed every hour to further increase system reliability.

Snoop Mode:

Selects between the three processor cache coherency snoop modes.

Energy Efficient Turbo:

Enables/disables the Intel Energy Efficient Turbo Boost type.

C1E:

Enables/disables the provision for the processor to switch to its minimum performance state when idle.

Collaborative CPU Performance Control:

Enables/disables the joint OS-System CPU power management control feature.

Memory Refresh Rate:

Selects the frequency at which the system memory controller performs the DRAM technology data refresh operation.

Uncore Frequency:

Selects the running frequency of the CPU internal uncore.

Energy Efficient Policy:

Selects amongst the CPU internal performance/power state weightings.

Monitor/Mwait:

Enables/disables use of the CPU opcodes defined to provide more efficient system software thread synchronization between multiple agents.

CPU Performance:

If supported by the CPU, Hardware P States is a performance-per-watt option that relies solely on the CPU to dynamically control individual core frequency.


Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/Intel-ic17.0-official-linux64-revD.html,
http://www.spec.org/cpu2017/flags/Dell-Platform-Flags-PowerEdge13G-revB.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/Intel-ic17.0-official-linux64-revD.xml,
http://www.spec.org/cpu2017/flags/Dell-Platform-Flags-PowerEdge13G-revB.xml.


For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2018 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v0.904.0.
Report generated on 2018-02-12 10:02:30 by SPEC CPU2017 flags formatter v5178.