CPU2017 Flag Description
Huawei Huawei 1288H V5 (Intel Xeon Platinum 8180)

Copyright © 2016 Intel Corporation. All Rights Reserved.


Base Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks


Peak Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks


Base Portability Flags

500.perlbench_r

502.gcc_r

505.mcf_r

520.omnetpp_r

523.xalancbmk_r

525.x264_r

531.deepsjeng_r

541.leela_r

548.exchange2_r

557.xz_r


Peak Portability Flags

500.perlbench_r

502.gcc_r

505.mcf_r

520.omnetpp_r

523.xalancbmk_r

525.x264_r

531.deepsjeng_r

541.leela_r

548.exchange2_r

557.xz_r


Base Optimization Flags

C benchmarks

C++ benchmarks

Fortran benchmarks


Peak Optimization Flags

C benchmarks

500.perlbench_r

502.gcc_r

505.mcf_r

525.x264_r

557.xz_r

C++ benchmarks

520.omnetpp_r

523.xalancbmk_r

531.deepsjeng_r

541.leela_r

Fortran benchmarks


Base Other Flags

C benchmarks

C++ benchmarks

Fortran benchmarks


Peak Other Flags

C benchmarks (except as noted below)

502.gcc_r

C++ benchmarks (except as noted below)

523.xalancbmk_r

Fortran benchmarks


Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.


Commands and Options Used to Submit Benchmark Runs

submit= MYMASK=`printf '0x%x' $((1<<$SPECCOPYNUM))`; /usr/bin/taskset $MYMASK $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command, using taskset, is used for Linux64 systems without numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:
submit= numactl --localalloc --physcpubind=$SPECCOPYNUM $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command is used for Linux64 systems with support for numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:

Shell, Environment, and Other Software Settings

numactl --interleave=all "runspec command"
Launching a process with numactl --interleave=all sets the memory interleave policy so that memory will be allocated using round robin on nodes. When memory cannot be allocated on the current interleave target fall back to other nodes.
KMP_STACKSIZE
Specify stack size to be allocated for each thread.
KMP_AFFINITY
Syntax: KMP_AFFINITY=[<modifier>,...]<type>[,<permute>][,<offset>]
The value for the environment variable KMP_AFFINITY affects how the threads from an auto-parallelized program are scheduled across processors.
It applies to binaries built with -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows).
modifier:
    granularity=fine Causes each OpenMP thread to be bound to a single thread context.
type:
    compact Specifying compact assigns the OpenMP thread <n>+1 to a free thread context as close as possible to the thread context where the <n> OpenMP thread was placed.
    scatter Specifying scatter distributes the threads as evenly as possible across the entire system.
permute: The permute specifier is an integer value controls which levels are most significant when sorting the machine topology map. A value for permute forces the mappings to make the specified number of most significant levels of the sort the least significant, and it inverts the order of significance.
offset: The offset specifier indicates the starting position for thread assignment.

Please see the Thread Affinity Interface article in the Intel Composer XE Documentation for more details.

Example: KMP_AFFINITY=granularity=fine,scatter
Specifying granularity=fine selects the finest granularity level and causes each OpenMP or auto-par thread to be bound to a single thread context.
This ensures that there is only one thread per core on cores supporting HyperThreading Technology
Specifying scatter distributes the threads as evenly as possible across the entire system.
Hence a combination of these two options, will spread the threads evenly across sockets, with one thread per physical core.

Example: KMP_AFFINITY=compact,1,0
Specifying compact will assign the n+1 thread to a free thread context as close as possible to thread n.
A default granularity=core is implied if no granularity is explicitly specified.
Specifying 1,0 sets permute and offset values of the thread assignment.
With a permute value of 1, thread n+1 is assigned to a consecutive core. With an offset of 0, the process's first thread 0 will be assigned to thread 0.
The same behavior is exhibited in a multisocket system.
OMP_NUM_THREADS
Sets the maximum number of threads to use for OpenMP* parallel regions if no other value is specified in the application. This environment variable applies to both -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores: export OMP_NUM_THREADS=8
Set stack size to unlimited
The command "ulimit -s unlimited" is used to set the stack size limit to unlimited.
Free the file system page cache
The command "echo 1> /proc/sys/vm/drop_caches" is used to free up the filesystem page cache.

Red Hat Specific features

Transparent Huge Pages
On RedHat EL 6 and later, Transparent Hugepages increase the memory page size from 4 kilobytes to 2 megabytes. Transparent Hugepages provide significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead.
Hugepages are used by default unless the /sys/kernel/mm/redhat_transparent_hugepage/enabled field is changed from its RedHat EL6 default of 'always'.

Operating System Tuning Parameters

Install only the relevant files

Select only test related files when installing the operating system,So that many services are not installed, this will reduce the consumption of resources by the operating system itself. In accordance with the following methods to install the operating system: 1.The software installation mode was selected 'Customize now'. 2.Next,In 'base System' column, We choose the following installation package,'Base','Compatibility Libraries', 'Java Platform','Large Systems Performance','Performance Tools','Perl Support'.In 'Development' column, We choose the following installation package,'Development tools'.That is all the installation package.

HUGETLB_MORECORE

Set this environment variable to "yes" to enable applications to use large pages.

LD_PRELOAD=/usr/lib64/libhugetlbfs.so

Setting this environment variable is necessary to enable applications to use large pages.

Cpufreq setting

"cpupower frequency-set" provides a simplified mechanism to adjust processor frequencies when cpu frequency scaling is enabled in the OS. See the cpupower-frequency-set man page for details.Here is a brief description of options used in the config file. By default, settings are applied to all logical cpus in the system.Frequencies can be passed in Hz, kHz (default), MHz, GHz, or THz by postfixing the value with the desired unit name, without any space. Available frequencies and governors can be determined with "cpupower frequency-info".

Tmpfs filesystem setting

Tmpfs is a file system which keeps all files in virtual memory.A tmpfs file system will go to swap if memory pressure demands real memory for applications. This can have a very negative effect on the I/O load and system performance

Process tuning setting

Each process is assigned a time period, known as its time slice, that is the time allowed to run the process. Increse the process time slice can have a positive effect on the calculated sensitivity task. The related kernel parameters are sched_wakeup_granularity_ns, sched_min_granularity_ns, etc.

Transparent Huge Pages

Transparent Hugepages increase the memory page size from 4 kilobytes to 2 megabytes. Transparent Hugepages provide significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead.

On RedHat EL6 and later, Transparent Hugepages are used by default if /sys/kernel/mm/redhat_transparent_hugepage/enabled is set to always. The default value is always.

On SUSE SLES11 and later, Transparent Hugepages are used by default if /sys/kernel/mm/transparent_hugepage/enabled is set to always. The default value is always.

Kernel Boot Parameter

nohz_full: This kernel option sets adaptive tick mode (NOHZ_FULL) to specified porcessors. Since the number of interrupts is reduced to ones per second, latency-sensitive applications can take advantage of it.


Firmware / BIOS / Microcode Settings

Hardware Prefetch:

This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Adjacent Sector Prefetch:

This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within a 128-byte sector that contains the data needed due to a cache line miss. In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Intel Turbo boost Technology:

Enabling this option allows the processor cores to automatically increase its frequency and increasing performance if it is running below power, temperature.

Intel Hyper Threading Technology:

Enabling this option allows to use processor resources more efficiently, enabling multiple threads to run on each core and increases processor throughput, improving overall performance on threaded software.

Power Policy Select (Default=Custom)

Values for this BIOS setting can be: Efficiency: Maximize the power efficiency of the server,Performance:Maximize the performance of the server, Custom:Allows the user to customize power and performance related options individually.

Lockstep Memory Mode (Default=Enabled)

Values for this BIOS setting can be: Lockstep memory mode uses two memory channels at a time and provides an even higher level of protection.You can adjust the mode to disabled.

cooling Configuration

The Baseboard Management Controller allows the user to adjust the fan speed manually,If the server is in a stressful environment, the CPU have high temperature, you can adjust the fan speed to 100%.

Memory Power Saving

Selects the memory power saving mode, Depends on the selected mode, the Power Down clock mode, CKE, and IBT are intialized accordingly, disable this featrue will keep memory in high performance mode.

C-State

Core C3, Core C6 can be disabled for latency-sensitive applications in order to minimize latency, but disable Core C-states can also significantly limit the amount of turbo when a low number of cores are active, C3 and C6 are recommended to enable in SPEC CPU benchmark.

VT Support

If virtualization is not used, this option should be set to "Disabled", this can result in slight performance liftings and energy savings

Memory Patrol Scrub

This BIOS option allows the enabling/disabling of Memory Periodic Patrol Scrubber. The Memory Periodic Patrol Scrubber corrects memory soft errors so that, over the length of the system runtime, the risk of producing multi-bit and uncorrectable errors is reduced.

IMC (Integrated memory controller) Interleaving

This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs), Memory could be interleaved across sockets, memory controllers, DDR channels, Ranks. Memory is interleaved for performance and thermal distribution.

If IMC Interleaving is set to 2-way, addresses will be interleaved between the two IMCs.

If IMC Interleaving is set to 1-way, there will be no interleaving.

If IMC Interleaving is set to auto, it depends on the SNC (Sub NUMA Clustering) setting, when SNC is set to enbaled, the IMC Interleaving will be 1-way interleave, SNC is set to disabled, the IMC Interleaving will be 2-way interleave.

If SNC is disabled, IMC Interleaving should be set to 2-way. If SNC is enabled, IMC Interleaving should be set to 1-way.

Sub NUMA Cluster(SNC)

SNC breaks up the last level cache (LLC) into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. SNC improves average latency to the LLC and memory. SNC is a replacement for the cluster on die (COD) feature found in previous processor families. For a multi-socketed system, all SNC clusters are mapped to unique NUMA (Non Uniform Memory Access) domains.

SNC AUTO supports 1-cluster or 2-clusters depending on IMC interleave. SNC and IMC interleave both AUTO will support 1-cluster 2-way IMC interleave.

SNC Enable supports Full SNC (2 clusters) and 1-way IMC interleave. Utilizes LLC capacity more efficiently and reduces latency due to core/IMC proximity. This may provide performance improvement on NUMA-aware operating systems.

SNC disable supports 1-cluster and 2-way IMC interleave, the LLC is treated as one cluster.

LLC Dead Line Allocation

In some Intel CPU caching schemes, mid-level cache (MLC) evictions are filled into the last level cache (LLC). If a line is evicted from the MLC to the LLC, the core can flag the evicted MLC lines as "dead.” This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if the option is disabled.

Values for this BIOS option can be:

Disabled: Disabling this option can save space in the LLC by never filling MLC dead lines into the LLC.

Enabled: Opportunistically fill MLC dead lines in LLC, if space is available.

Last Level Cache (LLC) Prefetch

This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit (DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.

Values for this BIOS option can be:

Disabled: Disables the LLC prefetcher. The other core prefetchers are unaffected.

Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.

Xtended Prediction Table (XPT) Prefetch

The Xtended Prediction Table (XPT) prefetcher exists on top of other prefetchers that can prefetch data into the DCU, MLC, and LLC. The XPT prefetcher will issue a speculative DRAM read request in parallel to an LLC lookup. This prefetch bypasses the LLC, saving latency. In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.

Values for this BIOS option can be:

Enabled: Allows a read request sent to the LLC to speculatively issue a copy of the read to DRAM.

Disabled: Read requests to the LLC are not allowed to send a speculative read to DRAM.


Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.html,
http://www.spec.org/cpu2017/flags/Huawei-Platform-Settings-SKL-V1.7.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.xml,
http://www.spec.org/cpu2017/flags/Huawei-Platform-Settings-SKL-V1.7.xml.


For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2018 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.0.2.
Report generated on 2018-02-12 11:10:12 by SPEC CPU2017 flags formatter v5178.