SPEC CPU®2017 Floating Point Rate Result

Copyright 2017-2020 Standard Performance Evaluation Corporation

Cisco Systems

Cisco UCS C220 M5 (Intel Xeon Gold 6150,
2.70 GHz)

SPECrate®2017_fp_base = 19600

SPECrate®2017_fp_peak = 20000
CPU2017 License: 9019 Test Date: Dec-2017
Test Sponsor: Cisco Systems Hardware Availability: Aug-2017
Tested by: Cisco Systems Software Availability: Sep-2017

Benchmark result graphs are available in the PDF report.

Hardware
CPU Name: Intel Xeon Gold 6150
  Max MHz: 3700
  Nominal: 2700
Enabled: 36 cores, 2 chips, 2 threads/core
Orderable: 1,2 Chips
Cache L1: 32 KB I + 32 KB D on chip per core
  L2: 1 MB I+D on chip per core
  L3: 24.75 MB I+D on chip per chip
  Other: None
Memory: 384 GB (24 x 16 GB 2Rx4 PC4-2666V-R)
Storage: 1 x 600 GB SAS HDD, 10K RPM
Other: None
Software
OS: SUSE Linux Enterprise Server 12 SP2 (x86_64)
4.4.21-69-default
Compiler: C/C++: Version 18.0.0.128 of Intel C/C++
Compiler for Linux;
Fortran: Version 18.0.0.128 of Intel Fortran
Compiler for Linux
Parallel: No
Firmware: Version 3.1.1d released Jun-2017
File System: xfs
System State: Run level 3 (multi-user)
Base Pointers: 64-bit
Peak Pointers: 64-bit
Other: None
Power Management: --

Results Table

Benchmark Base Peak
Copies Seconds Ratio Seconds Ratio Seconds Ratio Copies Seconds Ratio Seconds Ratio Seconds Ratio
SPECrate®2017_fp_base 19600
SPECrate®2017_fp_peak 20000
Results appear in the order in which they were run. Bold underlined text indicates a median measurement.
503.bwaves_r 72 1506 4790 1508 4790 1507 4790 72 1506 4790 1506 4790 1506 4800
507.cactuBSSN_r 72 500 1820 502 1820 503 1810 72 508 1800 507 1800 506 1800
508.namd_r 72 429 1590 426 1610 425 1610 72 421 1630 422 1620 422 1620
510.parest_r 72 1666 1130 1659 1140 1661 1130 72 1671 1130 1669 1130 1663 1130
511.povray_r 72 658 2560 659 2550 659 2550 72 558 3010 559 3010 557 3020
519.lbm_r 72 672 1130 672 1130 672 1130 72 645 1180 646 1170 647 1170
521.wrf_r 72 766 2100 763 2110 769 2100 72 766 2110 764 2110 763 2110
526.blender_r 72 495 2210 495 2210 495 2220 72 490 2240 491 2240 491 2230
527.cam4_r 72 544 2310 547 2300 545 2310 72 540 2330 540 2330 540 2330
538.imagick_r 72 526 3400 526 3400 527 3400 72 527 3400 526 3400 526 3400
544.nab_r 72 410 2960 409 2960 410 2960 72 401 3020 403 3000 400 3030
549.fotonik3d_r 72 1957 1430 1959 1430 1958 1430 72 1957 1430 1958 1430 1958 1430
554.roms_r 72 1278 89.5 1284 89.1 1279 89.5 72 1245 91.9 1237 92.5 1246 91.8

Submit Notes

 The taskset mechanism was used to bind copies to processors. The config file option 'submit'
 was used to generate taskset commands to bind each copy to a specific processor.
 For details, please see the config file.

Operating System Notes

 Stack size set to unlimited using "ulimit -s unlimited"

General Notes

Environment variables set by runcpu before the start of the run:
LD_LIBRARY_PATH = "/home/cpu2017/lib/ia32:/home/cpu2017/lib/intel64:/home/cpu2017/je5.0.1-32:/home/cpu2017/je5.0.1-64"

 Binaries compiled on a system with 1x Intel Core i7-4790 CPU + 32GB RAM
 memory using Redhat Enterprise Linux 7.4
 Transparent Huge Pages enabled by default
 Prior to runcpu invocation
 Filesystem page cache synced and cleared with:
 sync; echo 3>       /proc/sys/vm/drop_caches
No: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown)
is mitigated in the system as tested and documented.
No: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1)
is mitigated in the system as tested and documented.
No: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2)
is mitigated in the system as tested and documented.

This benchmark result is intended to provide perspective on
past performance using the historical hardware and/or
software described on this result page.

The system as described on this result page was formerly
generally available.  At the time of this publication, it may
not be shipping, and/or may not be supported, and/or may fail
to meet other tests of General Availability described in the
SPEC OSG Policy document, http://www.spec.org/osg/policy.html

This measured result may not be representative of the result
that would be measured were this benchmark run with hardware
and software available as of the publication date.

Platform Notes

BIOS Settings:
Intel HyperThreading Technology set to Enabled
CPU performance set to Enterprise
Power Performance Tuning set to OS Controls
SNC set to Enabled
IMC Interleaving set to 1-way Interleave
Patrol Scrub set to Disabled
 Sysinfo program /home/cpu2017/bin/sysinfo
 Rev: r5797 of 2017-06-14 96c45e4568ad54c135fd618bcc091c0f
 running on linux-a0tk Fri Dec 15 11:17:11 2017

 SUT (System Under Test) info as seen by some common utilities.
 For more information on this section, see
    https://www.spec.org/cpu2017/Docs/config.html#sysinfo

 From /proc/cpuinfo
    model name : Intel(R) Xeon(R) Gold 6150 CPU @ 2.70GHz
       2  "physical id"s (chips)
       72 "processors"
    cores, siblings (Caution: counting these is hw and system dependent. The following
    excerpts from /proc/cpuinfo might not be reliable.  Use with caution.)
       cpu cores : 18
       siblings  : 36
       physical 0: cores 0 1 2 3 4 8 9 10 11 16 17 18 19 20 24 25 26 27
       physical 1: cores 0 1 2 3 4 8 9 10 11 16 17 18 19 20 24 25 26 27

 From lscpu:
      Architecture:          x86_64
      CPU op-mode(s):        32-bit, 64-bit
      Byte Order:            Little Endian
      CPU(s):                72
      On-line CPU(s) list:   0-71
      Thread(s) per core:    2
      Core(s) per socket:    18
      Socket(s):             2
      NUMA node(s):          4
      Vendor ID:             GenuineIntel
      CPU family:            6
      Model:                 85
      Model name:            Intel(R) Xeon(R) Gold 6150 CPU @ 2.70GHz
      Stepping:              4
      CPU MHz:               1691.601
      CPU max MHz:           3700.0000
      CPU min MHz:           1200.0000
      BogoMIPS:              5387.31
      Virtualization:        VT-x
      L1d cache:             32K
      L1i cache:             32K
      L2 cache:              1024K
      L3 cache:              25344K
      NUMA node0 CPU(s):     0-2,5,6,9,10,14,15,36-38,41,42,45,46,50,51
      NUMA node1 CPU(s):     3,4,7,8,11-13,16,17,39,40,43,44,47-49,52,53
      NUMA node2 CPU(s):     18-20,23,24,27,28,32,33,54-56,59,60,63,64,68,69
      NUMA node3 CPU(s):     21,22,25,26,29-31,34,35,57,58,61,62,65-67,70,71
      Flags:                 fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
      pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp
      lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc
      aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg
      fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes
      xsave avx f16c rdrand lahf_lm abm 3dnowprefetch ida arat epb pln pts dtherm hwp
      hwp_act_window hwp_epp hwp_pkg_req intel_pt tpr_shadow vnmi flexpriority ept vpid
      fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx avx512f
      avx512dq rdseed adx smap clflushopt clwb avx512cd avx512bw avx512vl xsaveopt xsavec
      xgetbv1 cqm_llc cqm_occup_llc

 /proc/cpuinfo cache data
    cache size : 25344 KB

 From numactl --hardware  WARNING: a numactl 'node' might or might not correspond to a
 physical chip.
   available: 4 nodes (0-3)
   node 0 cpus: 0 1 2 5 6 9 10 14 15 36 37 38 41 42 45 46 50 51
   node 0 size: 95329 MB
   node 0 free: 94935 MB
   node 1 cpus: 3 4 7 8 11 12 13 16 17 39 40 43 44 47 48 49 52 53
   node 1 size: 96760 MB
   node 1 free: 96436 MB
   node 2 cpus: 18 19 20 23 24 27 28 32 33 54 55 56 59 60 63 64 68 69
   node 2 size: 96760 MB
   node 2 free: 96455 MB
   node 3 cpus: 21 22 25 26 29 30 31 34 35 57 58 61 62 65 66 67 70 71
   node 3 size: 96758 MB
   node 3 free: 96233 MB
   node distances:
   node   0   1   2   3
     0:  10  11  21  21
     1:  11  10  21  21
     2:  21  21  10  11
     3:  21  21  11  10

 From /proc/meminfo
    MemTotal:       394862732 kB
    HugePages_Total:       0
    Hugepagesize:       2048 kB

 /usr/bin/lsb_release -d
    SUSE Linux Enterprise Server 12 SP2

 From /etc/*release* /etc/*version*
    SuSE-release:
       SUSE Linux Enterprise Server 12 (x86_64)
       VERSION = 12
       PATCHLEVEL = 2
       # This file is deprecated and will be removed in a future service pack or release.
       # Please check /etc/os-release for details about this release.
    os-release:
       NAME="SLES"
       VERSION="12-SP2"
       VERSION_ID="12.2"
       PRETTY_NAME="SUSE Linux Enterprise Server 12 SP2"
       ID="sles"
       ANSI_COLOR="0;32"
       CPE_NAME="cpe:/o:suse:sles:12:sp2"

 uname -a:
    Linux linux-a0tk 4.4.21-69-default #1 SMP Tue Oct 25 10:58:20 UTC 2016 (9464f67)
    x86_64 x86_64 x86_64 GNU/Linux

 run-level 3 Dec 14 03:41

 SPEC is set to: /home/cpu2017
    Filesystem     Type  Size  Used Avail Use% Mounted on
    /dev/sda7      xfs   416G  116G  301G  28% /home

 Additional information from dmidecode follows.  WARNING: Use caution when you interpret
 this section. The 'dmidecode' program reads system data which is "intended to allow
 hardware to be accurately determined", but the intent may not be met, as there are
 frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard.
   BIOS Cisco Systems, Inc. C220M5.3.1.1d.0.0615170645 06/15/2017
   Memory:
    24x 0xCE00 M393A2G40EB2-CTD 16 GB 2 rank 2666

 (End of data from sysinfo program)

Compiler Version Notes

==============================================================================
C               | 519.lbm_r(base, peak) 538.imagick_r(base, peak)
                | 544.nab_r(base, peak)
------------------------------------------------------------------------------
icc (ICC) 18.0.0 20170811
Copyright (C) 1985-2017 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

==============================================================================
C++             | 508.namd_r(base, peak) 510.parest_r(base, peak)
------------------------------------------------------------------------------
icpc (ICC) 18.0.0 20170811
Copyright (C) 1985-2017 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

==============================================================================
C++, C          | 511.povray_r(base, peak) 526.blender_r(base, peak)
------------------------------------------------------------------------------
icpc (ICC) 18.0.0 20170811
Copyright (C) 1985-2017 Intel Corporation.  All rights reserved.
icc (ICC) 18.0.0 20170811
Copyright (C) 1985-2017 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

==============================================================================
C++, C, Fortran | 507.cactuBSSN_r(base, peak)
------------------------------------------------------------------------------
icpc (ICC) 18.0.0 20170811
Copyright (C) 1985-2017 Intel Corporation.  All rights reserved.
icc (ICC) 18.0.0 20170811
Copyright (C) 1985-2017 Intel Corporation.  All rights reserved.
ifort (IFORT) 18.0.0 20170811
Copyright (C) 1985-2017 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

==============================================================================
Fortran         | 503.bwaves_r(base, peak) 549.fotonik3d_r(base, peak)
                | 554.roms_r(base, peak)
------------------------------------------------------------------------------
ifort (IFORT) 18.0.0 20170811
Copyright (C) 1985-2017 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

==============================================================================
Fortran, C      | 521.wrf_r(base, peak) 527.cam4_r(base, peak)
------------------------------------------------------------------------------
ifort (IFORT) 18.0.0 20170811
Copyright (C) 1985-2017 Intel Corporation.  All rights reserved.
icc (ICC) 18.0.0 20170811
Copyright (C) 1985-2017 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

Base Compiler Invocation

C benchmarks:

 icc 

C++ benchmarks:

 icpc 

Fortran benchmarks:

 ifort 

Benchmarks using both Fortran and C:

 ifort   icc 

Benchmarks using both C and C++:

 icpc   icc 

Benchmarks using Fortran, C, and C++:

 icpc   icc   ifort 

Base Portability Flags

503.bwaves_r:  -DSPEC_LP64 
507.cactuBSSN_r:  -DSPEC_LP64 
508.namd_r:  -DSPEC_LP64 
510.parest_r:  -DSPEC_LP64 
511.povray_r:  -DSPEC_LP64 
519.lbm_r:  -DSPEC_LP64 
521.wrf_r:  -DSPEC_LP64   -DSPEC_CASE_FLAG   -convert big_endian 
526.blender_r:  -DSPEC_LP64   -DSPEC_LINUX   -funsigned-char 
527.cam4_r:  -DSPEC_LP64   -DSPEC_CASE_FLAG 
538.imagick_r:  -DSPEC_LP64 
544.nab_r:  -DSPEC_LP64 
549.fotonik3d_r:  -DSPEC_LP64 
554.roms_r:  -DSPEC_LP64 

Base Optimization Flags

C benchmarks:

 -xCORE-AVX2   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3 

C++ benchmarks:

 -xCORE-AVX2   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3 

Fortran benchmarks:

 -xCORE-AVX2   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3   -nostandard-realloc-lhs   -align array32byte 

Benchmarks using both Fortran and C:

 -xCORE-AVX2   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3   -nostandard-realloc-lhs   -align array32byte 

Benchmarks using both C and C++:

 -xCORE-AVX2   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3 

Benchmarks using Fortran, C, and C++:

 -xCORE-AVX2   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3   -nostandard-realloc-lhs   -align array32byte 

Base Other Flags

C benchmarks:

 -m64   -std=c11 

C++ benchmarks:

 -m64 

Fortran benchmarks:

 -m64 

Benchmarks using both Fortran and C:

 -m64   -std=c11 

Benchmarks using both C and C++:

 -m64   -std=c11 

Benchmarks using Fortran, C, and C++:

 -m64   -std=c11 

Peak Compiler Invocation

C benchmarks:

 icc 

C++ benchmarks:

 icpc 

Fortran benchmarks:

 ifort 

Benchmarks using both Fortran and C:

 ifort   icc 

Benchmarks using both C and C++:

 icpc   icc 

Benchmarks using Fortran, C, and C++:

 icpc   icc   ifort 

Peak Portability Flags

Same as Base Portability Flags

Peak Optimization Flags

C benchmarks:

519.lbm_r:  -prof-gen(pass 1)   -prof-use(pass 2)   -ipo   -xCORE-AVX2   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3 
538.imagick_r:  -xCORE-AVX2   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3 
544.nab_r:  Same as 519.lbm_r 

C++ benchmarks:

 -prof-gen(pass 1)   -prof-use(pass 2)   -ipo   -xCORE-AVX2   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3 

Fortran benchmarks:

503.bwaves_r:  -xCORE-AVX2   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3   -nostandard-realloc-lhs   -align array32byte 
549.fotonik3d_r:  Same as 503.bwaves_r 
554.roms_r:  -prof-gen(pass 1)   -prof-use(pass 2)   -ipo   -xCORE-AVX2   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3   -nostandard-realloc-lhs   -align array32byte 

Benchmarks using both Fortran and C:

 -prof-gen(pass 1)   -prof-use(pass 2)   -ipo   -xCORE-AVX2   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3   -nostandard-realloc-lhs   -align array32byte 

Benchmarks using both C and C++:

 -prof-gen(pass 1)   -prof-use(pass 2)   -ipo   -xCORE-AVX2   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3 

Benchmarks using Fortran, C, and C++:

 -prof-gen(pass 1)   -prof-use(pass 2)   -ipo   -xCORE-AVX2   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=3   -nostandard-realloc-lhs   -align array32byte 

Peak Other Flags

C benchmarks:

 -m64   -std=c11 

C++ benchmarks:

 -m64 

Fortran benchmarks:

 -m64 

Benchmarks using both Fortran and C:

 -m64   -std=c11 

Benchmarks using both C and C++:

 -m64   -std=c11 

Benchmarks using Fortran, C, and C++:

 -m64   -std=c11 

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.html,
http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.xml,
http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.xml.

SPEC CPU and SPECrate are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders.

For questions about this result, please contact the tester. For other inquiries, please contact info@spec.org
Copyright 2017-2020 Standard Performance Evaluation Corporation
Tested with SPEC CPU®2017 v1.0.2 on 2017-12-15 14:17:11-0500.
Report generated on 2020-08-05 15:29:53 by SPEC CPU®2017 HTML formatter v6255.
Originally published on 2018-02-23.