CPU2017 Flag Description
M Computers s.r.o. HPC S2600WFT (1.80 GHz, Intel Xeon Silver 4108)

Copyright © 2016 Intel Corporation. All Rights Reserved.


Base Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Base Portability Flags

503.bwaves_r

507.cactuBSSN_r

508.namd_r

510.parest_r

511.povray_r

519.lbm_r

521.wrf_r

526.blender_r

527.cam4_r

538.imagick_r

544.nab_r

549.fotonik3d_r

554.roms_r


Base Optimization Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Base Other Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.


Commands and Options Used to Submit Benchmark Runs

submit= MYMASK=`printf '0x%x' $((1<<$SPECCOPYNUM))`; /usr/bin/taskset $MYMASK $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command, using taskset, is used for Linux64 systems without numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:
submit= numactl --localalloc --physcpubind=$SPECCOPYNUM $command
When running multiple copies of benchmarks, the SPEC config file feature submit is used to cause individual jobs to be bound to specific processors. This specific submit command is used for Linux64 systems with support for numactl.
Here is a brief guide to understanding the specific command which will be found in the config file:

Shell, Environment, and Other Software Settings

numactl --interleave=all "runspec command"
Launching a process with numactl --interleave=all sets the memory interleave policy so that memory will be allocated using round robin on nodes. When memory cannot be allocated on the current interleave target fall back to other nodes.
KMP_STACKSIZE
Specify stack size to be allocated for each thread.
KMP_AFFINITY
Syntax: KMP_AFFINITY=[<modifier>,...]<type>[,<permute>][,<offset>]
The value for the environment variable KMP_AFFINITY affects how the threads from an auto-parallelized program are scheduled across processors.
It applies to binaries built with -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows).
modifier:
    granularity=fine Causes each OpenMP thread to be bound to a single thread context.
type:
    compact Specifying compact assigns the OpenMP thread <n>+1 to a free thread context as close as possible to the thread context where the <n> OpenMP thread was placed.
    scatter Specifying scatter distributes the threads as evenly as possible across the entire system.
permute: The permute specifier is an integer value controls which levels are most significant when sorting the machine topology map. A value for permute forces the mappings to make the specified number of most significant levels of the sort the least significant, and it inverts the order of significance.
offset: The offset specifier indicates the starting position for thread assignment.

Please see the Thread Affinity Interface article in the Intel Composer XE Documentation for more details.

Example: KMP_AFFINITY=granularity=fine,scatter
Specifying granularity=fine selects the finest granularity level and causes each OpenMP or auto-par thread to be bound to a single thread context.
This ensures that there is only one thread per core on cores supporting HyperThreading Technology
Specifying scatter distributes the threads as evenly as possible across the entire system.
Hence a combination of these two options, will spread the threads evenly across sockets, with one thread per physical core.

Example: KMP_AFFINITY=compact,1,0
Specifying compact will assign the n+1 thread to a free thread context as close as possible to thread n.
A default granularity=core is implied if no granularity is explicitly specified.
Specifying 1,0 sets permute and offset values of the thread assignment.
With a permute value of 1, thread n+1 is assigned to a consecutive core. With an offset of 0, the process's first thread 0 will be assigned to thread 0.
The same behavior is exhibited in a multisocket system.
OMP_NUM_THREADS
Sets the maximum number of threads to use for OpenMP* parallel regions if no other value is specified in the application. This environment variable applies to both -qopenmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows). Example syntax on a Linux system with 8 cores: export OMP_NUM_THREADS=8
Set stack size to unlimited
The command "ulimit -s unlimited" is used to set the stack size limit to unlimited.
Free the file system page cache
The command "echo 1> /proc/sys/vm/drop_caches" is used to free up the filesystem page cache.

Red Hat Specific features

Transparent Huge Pages
On RedHat EL 6 and later, Transparent Hugepages increase the memory page size from 4 kilobytes to 2 megabytes. Transparent Hugepages provide significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead.
Hugepages are used by default unless the /sys/kernel/mm/redhat_transparent_hugepage/enabled field is changed from its RedHat EL6 default of 'always'.

Firmware / BIOS / Microcode Settings

Intel(R) Hyper-Threading Tech:
Intel(R) Hyper-Threading Technology allows multithreaded software applications to execute threads in parallel within each processor. Can be [Enabled] or [Disabled].
Active Processor Cores:
Number of cores to enable in each processor package. Can be set from [1] to [all].
Execute Disable Bit:
Can help prevent certain classes of malicious buffer overflow attacks. Can be [Enabled] or [Disabled].
Intel(R) Virtualization Technology:
Allows a platform to run multiple operating systems and applications in independent partitions. Can be [Enabled] or [Disabled].
Enhanced Error Containment Mode:
Enable Enhanced Error Containment Mode(Data Poisoning) - Erroneous data coming from memory will be poisoned. If disabled(default), will be in legacy Mode - No data poisoning support available.
MLC Streamer:
Memory Latency Checker (MLC) Streamer is a speculative prefetch unit within the processor(s). Can be [Enabled] or [Disabled].
MLC Spatial Prefetcher :
[Enabled] Fetches adjacent cache line (128 bytes) when required data is not currently in cache [Disabled] Only fetches cache line with data required by the processor (64 bytes)
L1-data cache (DCU) Data Prefetcher:
[Enabled] The next cache line will be prefetched into L1 data cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data [Disabled] Only fetches cache line with data required by the processor (64 bytes)
L1-data cache (DCU) Instruction Prefetcher:
The next cache line will be prefetched into L1 instruction cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. Can be [Enabled] or [Disabled].
LLC Prefetch:
Last Level Cache (LLC) Prefetcher. Can be [Enabled] or [Disabled].
CPU and Power Performance Policy:
Allows the user to set an overall power and performance policy for the system, and when changed will modify a selected list of options to achieve the policy. These options are still changeable outside of the policy but do reflect the changes that the policy makes when a new policy is selected. [Performance] - Optimization is strongly toward performance, even at the expense of energy efficiency [Balanced Performance] - Weights optimization towards performance, while conserving energy [Balanced Power] - Weights optimization towards energy conservation, with good performance [Power] - Optimization is strongly toward energy efficiency, even at the expense of performance
Workload Configuration:
Controls the aggressiveness of the energy performance BIAS settings. This bit field allows the Basic Input-Output System (BIOS) to choose a configuration that may improve performance on certain workloads. Can be [Balanced] or [I/O Sensitive].
Uncore Frequency Scaling:
Allows the voltage and frequency of Uncore to be programmed independently. The Uncore activity is monitored to optimize the frequency in real-time. Can be [Enabled] or [Disabled].
Performance P-limit:
Allows the Uncore frequency coordination of two processors. Can be [Enabled] or [Disabled].
Enhanced Intel SpeedStep(R) Tech:
Allows the system to dynamically adjust processor voltage and core frequency, which can result in decreased average power consumption and decreased average heat production. Can be [Enabled] or [Disabled].
Intel(R) Turbo Boost Technology:
Allows the processor to automatically increase its frequency if it is running below power, temperature and current specifications. Can be [Enabled] or [Disabled].
Energy Efficient Turbo:
When Energy Efficient Turbo is enabled, the Central Processing Unit (CPU) cores only enter the turbo frequency when the Power Control Unit (PCU) detects high utilization.
CPU C-State:
When Central Processing Unit (CPU) C-State is enabled, the Central Processing Unit (CPU) cores enter the sleep state when there is no loading on it. Can be [Enabled] or [Disabled].
Package C-State:
Set and specifies the lowest C-state for Processor package. [C0/C1 state] - No C-state package support [C2 state] [C6(non Retention) state] [C6(Retention) state] - Provides more power saving than C6 non retention state [No limit] - No C-state package limit
C1E Autopromote:
[Enabled] - the Central Processing Unit (CPU) will switch to the minimum Enhanced Intel SpeedStep(R) Technology operating point when all execution cores enter C1. Frequency will switch immediately, followed by gradual Voltage switching. [Disabled] - the Central Processing Unit (CPU) will not transit to the minimum Enhanced Intel SpeedStep(R) Technology operating point when all execution cores enter C1.
Processor C6:
Processor reports C6 state to Operating System (OS). Can be [Enabled] or [Disabled].
Hardware P-states:
[Disable] - Hardware chooses a P-state based on Operating System (OS) Request (Legacy P-states) [Native Mode] - Hardware chooses a P-state based on Operating System (OS) guidance [Out of Band Mode] - Hardware autonomously chooses a P-state (no Operating System (OS) guidance) [Native Mode with No Legacy Support]
Intel(R) UPI Frequency Select:
Allows for selecting the Intel(R) UltraPath Interconnect (UPI) Frequency. Recommended to leave in [Auto Max] so that the Basic Input-Output System (BIOS) can select the highest common Intel(R) UltraPath Interconnect Frequency. Can be set [8.0GT/s], [9.6GT/s], [10.4GT/s] or [Auto Max].
IMC Interleaving:
Integrated Memory Controller (IMC) interleaving. Can be set [Auto], [1-way interleaving] or [2-way interleaving].
Mirror Mode:
Allows the user to select the Mirror Mode to be applied for the next boot. Two-level memory (2LM) will be hidden when AEPDimm is not present.
ADDDC Sparing:
Can [Enable] or [Disable] Adaptive Double Device Data Correction (ADDDC) Sparing.
Memory sparing:
Can [Enable] or [Disable] Memory Rank Sparing.
NUMA Optimized:
If enabled, the Basic Input-Output System (BIOS) includes Advanced Configuration and Power Interface (ACPI) tables that are required for Non-Uniform Memory Access (NUMA)-aware Operating Systems.
Sub_NUMA Cluster:
When enabled, sub Non-Uniform Memory Access (NUMA) cluster is enabled. If any memory controller has no memory attached, this feature cannot be enabled.
Patrol Scrub:
When enabled, performs periodic checks on memory cells and proactively walks through populated memory space, to seek and correct soft Error Checking and Correcting (ECC) errors.
Memory Correctable Error:
When enabled, allow memory correctable error to trigger System Management Interrupt (SMI) and log into System Event Log (SEL).
Set Fan Profile:
[Performance] Fan control provides primary system cooling before attempting to throttle memory [Acoustic] The system will favor using throttling of memory over boosting fans to cool the system if thermal thresholds are met
Fan PWM Offset:
Valid Offset 0-100. This number is added to the calculated Pulse-Width Modulation (PWM) value to increase Fan Speed.

Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.2017-10-19.html,
http://www.spec.org/cpu2017/flags/MComputers-Platform-Settings-SKL-revA.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.2017-10-19.xml,
http://www.spec.org/cpu2017/flags/MComputers-Platform-Settings-SKL-revA.xml.


For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2018 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.0.2.
Report generated on 2018-10-31 16:12:53 by SPEC CPU2017 flags formatter v5178.