CPU2017 Flag Description
Lenovo Global Technology ThinkSystem SR665 2.00 GHz, AMD EPYC 7702

Compilers: AMD Optimizing C/C++ Compiler Suite


Base Compiler Invocation

C benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using Fortran, C, and C++


Peak Compiler Invocation

C benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using Fortran, C, and C++


Base Portability Flags

603.bwaves_s

607.cactuBSSN_s

619.lbm_s

621.wrf_s

627.cam4_s

628.pop2_s

638.imagick_s

644.nab_s

649.fotonik3d_s

654.roms_s


Peak Portability Flags

603.bwaves_s

607.cactuBSSN_s

619.lbm_s

621.wrf_s

627.cam4_s

628.pop2_s

638.imagick_s

644.nab_s

649.fotonik3d_s

654.roms_s


Base Optimization Flags

C benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using Fortran, C, and C++


Peak Optimization Flags

C benchmarks

619.lbm_s

638.imagick_s

644.nab_s

Fortran benchmarks

603.bwaves_s

649.fotonik3d_s

654.roms_s

Benchmarks using both Fortran and C

621.wrf_s

627.cam4_s

628.pop2_s

Benchmarks using Fortran, C, and C++


Base Other Flags

C benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using Fortran, C, and C++


Peak Other Flags

C benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using Fortran, C, and C++


Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.


Commands and Options Used to Submit Benchmark Runs

Using numactl to bind processes and memory to cores

For multi-copy runs or single copy runs on systems with multiple sockets, it is advantageous to bind a process to a particular core. Otherwise, the OS may arbitrarily move your process from one core to another. This can affect performance. To help, SPEC allows the use of a "submit" command where users can specify a utility to use to bind processes. We have found the utility 'numactl' to be the best choice.

numactl runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a command and inherited by all of its children. The numactl flag "--physcpubind" specifies which core(s) to bind the process. "-l" instructs numactl to keep a process's memory on the local node while "-m" specifies which node(s) to place a process's memory. For full details on using numactl, please refer to your Linux documentation, 'man numactl'

Note that some older versions of numactl incorrectly interpret application arguments as its own. For example, with the command "numactl --physcpubind=0 -l a.out -m a", numactl will interpret a.out's "-m" option as its own "-m" option. To work around this problem, we put the command to be run in a shell script and then run the shell script using numactl. For example: "echo 'a.out -m a' > run.sh ; numactl --physcpubind=0 bash run.sh"


Shell, Environment, and Other Software Settings

Transparent Huge Pages (THP)

THP is an abstraction layer that automates most aspects of creating, managing, and using huge pages. THP is designed to hide much of the complexity in using huge pages from system administrators and developers, as normal huge pages must be assigned at boot time, can be difficult to manage manually, and often require significant changes to code in order to be used effectively. Most recent Linux OS releases have THP enabled by default.

Linux Huge Page settings

If you need finer control you can manually set huge pages using the following steps:

Note that further information about huge pages may be found in the Linux kernel documentation file hugetlbpage.txt.

ulimit -s <n>

Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.

ulimit -l <n>

Sets the maximum size of memory that may be locked into physical memory.

powersave -f (on SuSE)

Makes the powersave daemon set the CPUs to the highest supported frequency.

/etc/init.d/cpuspeed stop (on Red Hat)

Disables the cpu frequency scaling program in order to set the CPUs to the highest supported frequency.

LD_LIBRARY_PATH

An environment variable that indicates the location in the filesystem of bundled libraries to use when running the benchmark binaries.

kernel/randomize_va_space

This option can be used to select the type of process address space randomization that is used in the system, for architectures that support this feature.

MALLOC_CONF

An environment variable set to tune the jemalloc allocation strategy during the execution of the binaries. This environment variable setting is not needed when building the binaries on the system under test.


Operating System Tuning Parameters

sched_cfs_bandwidth_slice_us
This OS setting controls the amount of run-time(bandwidth) transferred to a run queue from the task's control group bandwidth pool. Small values allow the global bandwidth to be shared in a fine-grained manner among tasks, larger values reduce transfer overhead. The default value is 5000 (ns).
sched_latency_ns
This OS setting configures targeted preemption latency for CPU bound tasks. The default value is 24000000 (ns).
sched_migration_cost_ns
Amount of time after the last execution that a task is considered to be "cache hot" in migration decisions. A "hot" task is less likely to be migrated to another CPU, so increasing this variable reduces task migrations. The default value is 500000 (ns).
sched_min_granularity_ns
This OS setting controls the minimal preemption granularity for CPU bound tasks. As the number of runnable tasks increases, CFS(Complete Fair Scheduler), the scheduler of the Linux kernel, decreases the timeslices of tasks. If the number of runnable tasks exceeds sched_latency_ns/sched_min_granularity_ns, the timeslice becomes number_of_running_tasks * sched_min_granularity_ns. The default value is 8000000 (ns).
sched_wakeup_granularity_ns
This OS setting controls the wake-up preemption granularity. Increasing this variable reduces wake-up preemption, reducing disturbance of compute bound tasks. Lowering it improves wake-up latency and throughput for latency critical tasks, particularly when a short duty cycle load component must compete with CPU bound components. The default value is 10000000 (ns).
numa_balancing
This OS setting controls automatic NUMA balancing on memory mapping and process placement. Setting 0 disables this feature. It is enabled by default (1).

Firmware / BIOS / Microcode Settings

Choose Operating Mode: (Default="Maximum Efficiency")
Select the operating mode based on your preference. Note, power savings and performance are also highly dependent on hardware and software running on system.
Determinism Slider:
Global C-state Control:
Controls IO based C-state generation and DF C-states.
cTDP:
Sets the maximum power consumption for CPU. cTDP is only configurable before OS boot.
cTDP Manual:
cTDP is the acronym for Configurable TDP. Some Rome CPU skus support a default TDP and a higher cTDP expressed in Watts. Model Normal TDP Minimum cTDP Maximum cTDP EPYC 7H12 280 225 280 EPYC 7742 225 225 240 EPYC 7702 200 165 200 EPYC 7702P 200 165 200 EPYC 7662 225 225 240 EPYC 7642 225 225 240 EPYC 7502 180 165 200 EPYC 7502P 180 165 200 EPYC 7542 225 225 240 EPYC 7402 180 165 200 EPYC 7402P 180 165 200 EPYC 7302 155 155 180 EPYC 7302P 155 155 180 EPYC 7252 120 120 150
Memory Speed:
Select the desired memory speed. Faster speeds offer better performance but consume more power.
NUMA nodes per socket:
Specifies the number of desired NUMA nodes per socket. Zero will attempt to interleave the two sockets together.
Package Power Limit Control:
Auto = Use the fused PPT\nManual = User can set customized PPT\n***PPT will be used as the ASIC power limit***
SMT Mode:
Can be used to disable symmetric multithreading. To re-enable SMT, a POWER CYCLE is needed after selecting Enable.
CCD Control:
Sets the number of CCDs to be used. Once this option has been used to remove any CCDs, a POWER CYCLE is required in order for future selections to take effect.
Efficiency Mode:
This setting enables an energy efficient mode of operation internal to AMD EPYC Gen2 processors at the expense of performance. The settings should be enabled when energy efficient operation is desired from the processor.
LCC as NUMA Node:
Exposes the processor's last level caches as NUMA nodes. When enabled, can improve performance for highly NUMA optimized workloads if workloads or components of workloads can be pinned into the caches.
Zero Output:
When zero output is set to 'Advanced mode' and multiple power supplies are installed in the server, some of the PSUs will be automatically placed into a low power state under light load conditions. This helps to save power
SOC P-states:
When Auto is selected the CPU SOC P-states(uncore P-states) will be dynamically adjusted. That is, their frequency will dynamically change based on the workload. Selecting P0, P1, P2, or P3 forces the SOC to a specific P-state frequency.
L1 Stream HW Prefetcher:
Enable/Disable L1 Stream HW Prefetcher. Fetches the next cache line int to the L1 cache when cached lines are reused within a certain time period or accessed sequentially.
L2 Stream HW Prefetcher:
Enable/Disable L2 Stream HW Prefetcher. Fetches the next cache line int to the L2 cache when cached lines are reused within a certain time period or accessed sequentially.

Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/aocc200-flags-B1-1.html,
http://www.spec.org/cpu2017/flags/Lenovo-Platform-SPECcpu2017-Flags-V1.2-Rome2P-J.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/aocc200-flags-B1-1.xml,
http://www.spec.org/cpu2017/flags/Lenovo-Platform-SPECcpu2017-Flags-V1.2-Rome2P-J.xml.


For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2020 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.1.0.
Report generated on 2020-05-05 11:00:29 by SPEC CPU2017 flags formatter v5178.