SPEC CPU®2017 Floating Point Speed Result

Copyright 2017-2020 Standard Performance Evaluation Corporation

Tyrone Systems (Test Sponsor: Netweb Pte Ltd)

DIT400TR-55RL
(2.10 GHz, Intel Xeon Gold 5218R)

SPECspeed®2017_fp_base = 12100

SPECspeed®2017_fp_peak = 12200

CPU2017 License: 006042 Test Date: Oct-2020
Test Sponsor: Netweb Pte Ltd Hardware Availability: Aug-2020
Tested by: Tyrone Systems Software Availability: Jun-2020

Benchmark result graphs are available in the PDF report.

Hardware
CPU Name: Intel Xeon Gold 5218R
  Max MHz: 4000
  Nominal: 2100
Enabled: 40 cores, 2 chips, 2 threads/core
Orderable: 1,2 (chip)s
Cache L1: 32 KB I + 32 KB D on chip per core
  L2: 1 MB I+D on chip per core
  L3: 27.5 MB I+D on chip per chip
  Other: None
Memory: 384 GB (12 x 32 GB 2Rx4 PC4-2933P-R)
Storage: 1 x 480 GB SATA SSD
Other: None
Software
OS: CentOS Linux release 8.2.2004 (Core)
4.18.0-193.el8.x86_64
Compiler: C/C++: Version 19.1.1.217 of Intel C/C++ Compiler
Compiler Build 20200306 for Linux;
Fortran: Version 19.1.1.217 of Intel Fortran
Compiler Build 20200306 for Linux
Parallel: Yes
Firmware: Version V8.102 released Jun-2020
File System: xfs
System State: Run level 3 (multi-user)
Base Pointers: 64-bit
Peak Pointers: 64-bit
Other: jemalloc memory allocator V5.0.1
Power Management: Default

Results Table

Benchmark Base Peak
Threads Seconds Ratio Seconds Ratio Seconds Ratio Threads Seconds Ratio Seconds Ratio Seconds Ratio
SPECspeed®2017_fp_base 12100
SPECspeed®2017_fp_peak 12200
Results appear in the order in which they were run. Bold underlined text indicates a median measurement.
603.bwaves_s 40 1290 4590 1310 4520 1290 4570 40 1290 4570 1300 4550 1310 4510
607.cactuBSSN_s 40 1160 1440 1180 1410 1180 1420 40 1160 1440 1180 1410 1180 1420
619.lbm_s 40 60.0 87.3 58.8 89.1 58.8 89.0 40 60.0 87.3 58.8 89.1 58.8 89.0
621.wrf_s 40 1140 1160 1150 1150 1150 1150 40 1090 1220 1090 1220 1090 1220
627.cam4_s 40 97.6 90.8 97.9 90.5 97.4 91.0 40 97.6 90.8 97.9 90.5 97.4 91.0
628.pop2_s 40 1870 63.5 1830 64.7 1840 64.5 40 1870 63.5 1830 64.7 1840 64.5
638.imagick_s 40 1710 84.6 1710 84.2 1710 84.3 40 1710 84.6 1710 84.2 1710 84.3
644.nab_s 40 83.5 2090 83.7 2090 83.6 2090 80 79.4 2200 79.3 2200 79.1 2210
649.fotonik3d_s 40 1140 80.0 1120 81.4 1110 82.5 40 1120 81.7 1110 82.4 1110 82.2
654.roms_s 40 1350 1160 1360 1160 1340 1170 40 1350 1160 1360 1160 1340 1170

Operating System Notes

 Stack size set to unlimited using "ulimit -s unlimited"

Environment Variables Notes

Environment variables set by runcpu before the start of the run:
KMP_AFFINITY = "granularity=fine,compact,1,0"
LD_LIBRARY_PATH = "/home/cpu2017/lib/intel64:/home/cpu2017/je5.0.1-64"
MALLOC_CONF = "retain:true"
OMP_STACKSIZE = "192M"

General Notes

 Binaries compiled on a system with 2x Intel Xeon 4214R CPU + 384GB RAM
 memory using Centos 8.2 x86_64
 Transparent Huge Pages enabled by default
 Prior to runcpu invocation
 Filesystem page cache synced and cleared with:
 sync; echo 3>       /proc/sys/vm/drop_caches
 NA: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown)
 is mitigated in the system as tested and documented.
 Yes: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1)
 is mitigated in the system as tested and documented.
 Yes: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2)
 is mitigated in the system as tested and documented.
 jemalloc, a general purpose malloc implementation
 built with the RedHat Enterprise 7.5, and the system compiler gcc 4.8.5
 sources available from jemalloc.net or https://github.com/jemalloc/jemalloc/releases

Platform Notes


 Sysinfo program /home/cpu2017/bin/sysinfo
 Rev: r6365 of 2019-08-21 295195f888a3d7edb1e6e46a485a0011
 running on localhost.localdomain Sun Oct 11 00:28:04 2020

 SUT (System Under Test) info as seen by some common utilities.
 For more information on this section, see
    https://www.spec.org/cpu2017/Docs/config.html#sysinfo

 From /proc/cpuinfo
    model name : Intel(R) Xeon(R) Gold 5218R CPU @ 2.10GHz
       2  "physical id"s (chips)
       80 "processors"
    cores, siblings (Caution: counting these is hw and system dependent. The following
    excerpts from /proc/cpuinfo might not be reliable.  Use with caution.)
       cpu cores : 20
       siblings  : 40
       physical 0: cores 0 1 2 3 4 8 9 10 11 12 16 17 18 19 20 24 25 26 27 28
       physical 1: cores 0 1 2 3 4 8 9 10 11 12 16 17 18 19 20 24 25 26 27 28

 From lscpu:
      Architecture:        x86_64
      CPU op-mode(s):      32-bit, 64-bit
      Byte Order:          Little Endian
      CPU(s):              80
      On-line CPU(s) list: 0-79
      Thread(s) per core:  2
      Core(s) per socket:  20
      Socket(s):           2
      NUMA node(s):        2
      Vendor ID:           GenuineIntel
      CPU family:          6
      Model:               85
      Model name:          Intel(R) Xeon(R) Gold 5218R CPU @ 2.10GHz
      Stepping:            7
      CPU MHz:             3214.618
      CPU max MHz:         4000.0000
      CPU min MHz:         800.0000
      BogoMIPS:            4200.00
      Virtualization:      VT-x
      L1d cache:           32K
      L1i cache:           32K
      L2 cache:            1024K
      L3 cache:            28160K
      NUMA node0 CPU(s):   0-19,40-59
      NUMA node1 CPU(s):   20-39,60-79
      Flags:               fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
      pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp
      lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid
      aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16
      xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave
      avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3
      invpcid_single intel_ppin ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi
      flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm
      cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd
      avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total
      cqm_mbm_local dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req pku
      ospke avx512_vnni md_clear flush_l1d arch_capabilities

 /proc/cpuinfo cache data
    cache size : 28160 KB

 From numactl --hardware  WARNING: a numactl 'node' might or might not correspond to a
 physical chip.
   available: 2 nodes (0-1)
   node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 40 41 42 43 44 45 46 47
   48 49 50 51 52 53 54 55 56 57 58 59
   node 0 size: 192103 MB
   node 0 free: 151937 MB
   node 1 cpus: 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 60 61 62 63 64
   65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
   node 1 size: 193499 MB
   node 1 free: 168391 MB
   node distances:
   node   0   1
     0:  10  21
     1:  21  10

 From /proc/meminfo
    MemTotal:       394857704 kB
    HugePages_Total:       0
    Hugepagesize:       2048 kB

 From /etc/*release* /etc/*version*
    centos-release: CentOS Linux release 8.2.2004 (Core)
    centos-release-upstream: Derived from Red Hat Enterprise Linux 8.2 (Source)
    os-release:
       NAME="CentOS Linux"
       VERSION="8 (Core)"
       ID="centos"
       ID_LIKE="rhel fedora"
       VERSION_ID="8"
       PLATFORM_ID="platform:el8"
       PRETTY_NAME="CentOS Linux 8 (Core)"
       ANSI_COLOR="0;31"
    redhat-release: CentOS Linux release 8.2.2004 (Core)
    system-release: CentOS Linux release 8.2.2004 (Core)
    system-release-cpe: cpe:/o:centos:centos:8

 uname -a:
    Linux localhost.localdomain 4.18.0-193.el8.x86_64 #1 SMP Fri May 8 10:59:10 UTC 2020
    x86_64 x86_64 x86_64 GNU/Linux

 Kernel self-reported vulnerability status:

 itlb_multihit:                            KVM: Mitigation: Split huge pages
 CVE-2018-3620 (L1 Terminal Fault):        Not affected
 Microarchitectural Data Sampling:         Not affected
 CVE-2017-5754 (Meltdown):                 Not affected
 CVE-2018-3639 (Speculative Store Bypass): Mitigation: Speculative Store Bypass disabled
                                           via prctl and seccomp
 CVE-2017-5753 (Spectre variant 1):        Mitigation: usercopy/swapgs barriers and __user
                                           pointer sanitization
 CVE-2017-5715 (Spectre variant 2):        Mitigation: Enhanced IBRS, IBPB: conditional,
                                           RSB filling
 tsx_async_abort:                          Mitigation: Clear CPU buffers; SMT vulnerable

 run-level 3 Oct 9 02:24

 SPEC is set to: /home/cpu2017
    Filesystem          Type  Size  Used Avail Use% Mounted on
    /dev/mapper/cl-home xfs   392G  115G  278G  30% /home

 From /sys/devices/virtual/dmi/id
     BIOS:    American Megatrends Inc. V8.102 06/09/2020
     Vendor:  Tyrone Systems
     Product: TP12XH-L2I
     Product Family: empty
     Serial:  empty

 Additional information from dmidecode follows.  WARNING: Use caution when you interpret
 this section. The 'dmidecode' program reads system data which is "intended to allow
 hardware to be accurately determined", but the intent may not be met, as there are
 frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard.
   Memory:
     12x Samsung M393A4K40CB2-CVF 32 GB 2 rank 2933

 (End of data from sysinfo program)

Compiler Version Notes

==============================================================================
C               | 619.lbm_s(base, peak) 638.imagick_s(base, peak)
                | 644.nab_s(base, peak)
------------------------------------------------------------------------------
Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64,
  Version 19.1.1.217 Build 20200306
Copyright (C) 1985-2020 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

==============================================================================
C++, C, Fortran | 607.cactuBSSN_s(base, peak)
------------------------------------------------------------------------------
Intel(R) C++ Intel(R) 64 Compiler for applications running on Intel(R) 64,
  Version 19.1.1.217 Build 20200306
Copyright (C) 1985-2020 Intel Corporation.  All rights reserved.
Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64,
  Version 19.1.1.217 Build 20200306
Copyright (C) 1985-2020 Intel Corporation.  All rights reserved.
Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R)
  64, Version 19.1.1.217 Build 20200306
Copyright (C) 1985-2020 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

==============================================================================
Fortran         | 603.bwaves_s(base, peak) 649.fotonik3d_s(base, peak)
                | 654.roms_s(base, peak)
------------------------------------------------------------------------------
Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R)
  64, Version 19.1.1.217 Build 20200306
Copyright (C) 1985-2020 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

==============================================================================
Fortran, C      | 621.wrf_s(base, peak) 627.cam4_s(base, peak)
                | 628.pop2_s(base, peak)
------------------------------------------------------------------------------
Intel(R) Fortran Intel(R) 64 Compiler for applications running on Intel(R)
  64, Version 19.1.1.217 Build 20200306
Copyright (C) 1985-2020 Intel Corporation.  All rights reserved.
Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64,
  Version 19.1.1.217 Build 20200306
Copyright (C) 1985-2020 Intel Corporation.  All rights reserved.
------------------------------------------------------------------------------

Base Compiler Invocation

C benchmarks:

 icc 

Fortran benchmarks:

 ifort 

Benchmarks using both Fortran and C:

 ifort   icc 

Benchmarks using Fortran, C, and C++:

 icpc   icc   ifort 

Base Portability Flags

603.bwaves_s:  -DSPEC_LP64 
607.cactuBSSN_s:  -DSPEC_LP64 
619.lbm_s:  -DSPEC_LP64 
621.wrf_s:  -DSPEC_LP64   -DSPEC_CASE_FLAG   -convert big_endian 
627.cam4_s:  -DSPEC_LP64   -DSPEC_CASE_FLAG 
628.pop2_s:  -DSPEC_LP64   -DSPEC_CASE_FLAG   -convert big_endian   -assume byterecl 
638.imagick_s:  -DSPEC_LP64 
644.nab_s:  -DSPEC_LP64 
649.fotonik3d_s:  -DSPEC_LP64 
654.roms_s:  -DSPEC_LP64 

Base Optimization Flags

C benchmarks:

 -m64   -std=c11   -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=4   -qopenmp   -DSPEC_OPENMP   -mbranches-within-32B-boundaries 

Fortran benchmarks:

 -m64   -Wl,-z,muldefs   -DSPEC_OPENMP   -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=4   -qopenmp   -nostandard-realloc-lhs   -mbranches-within-32B-boundaries   -L/usr/local/je5.0.1-64/lib   -ljemalloc 

Benchmarks using both Fortran and C:

 -m64   -std=c11   -Wl,-z,muldefs   -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=4   -qopenmp   -DSPEC_OPENMP   -mbranches-within-32B-boundaries   -nostandard-realloc-lhs   -L/usr/local/je5.0.1-64/lib   -ljemalloc 

Benchmarks using Fortran, C, and C++:

 -m64   -std=c11   -Wl,-z,muldefs   -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=4   -qopenmp   -DSPEC_OPENMP   -mbranches-within-32B-boundaries   -nostandard-realloc-lhs   -L/usr/local/je5.0.1-64/lib   -ljemalloc 

Peak Compiler Invocation

C benchmarks:

 icc 

Fortran benchmarks:

 ifort 

Benchmarks using both Fortran and C:

 ifort   icc 

Benchmarks using Fortran, C, and C++:

 icpc   icc   ifort 

Peak Portability Flags

Same as Base Portability Flags

Peak Optimization Flags

C benchmarks:

619.lbm_s:  basepeak = yes 
638.imagick_s:  basepeak = yes 
644.nab_s:  -m64   -std=c11   -Wl,-z,muldefs   -xCORE-AVX512   -ipo   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=4   -qopenmp   -DSPEC_OPENMP   -mbranches-within-32B-boundaries   -L/usr/local/je5.0.1-64/lib   -ljemalloc 

Fortran benchmarks:

603.bwaves_s:  -m64   -Wl,-z,muldefs   -prof-gen(pass 1)   -prof-use(pass 2)   -DSPEC_SUPPRESS_OPENMP   -DSPEC_OPENMP   -ipo   -xCORE-AVX512   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=4   -qopenmp   -nostandard-realloc-lhs   -mbranches-within-32B-boundaries   -L/usr/local/je5.0.1-64/lib   -ljemalloc 
649.fotonik3d_s:  Same as 603.bwaves_s 
654.roms_s:  basepeak = yes 

Benchmarks using both Fortran and C:

621.wrf_s:  -m64   -std=c11   -Wl,-z,muldefs   -prof-gen(pass 1)   -prof-use(pass 2)   -ipo   -xCORE-AVX512   -O3   -no-prec-div   -qopt-prefetch   -ffinite-math-only   -qopt-mem-layout-trans=4   -DSPEC_SUPPRESS_OPENMP   -qopenmp   -DSPEC_OPENMP   -mbranches-within-32B-boundaries   -nostandard-realloc-lhs   -L/usr/local/je5.0.1-64/lib   -ljemalloc 
627.cam4_s:  basepeak = yes 
628.pop2_s:  basepeak = yes 

Benchmarks using Fortran, C, and C++:

607.cactuBSSN_s:  basepeak = yes 

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/Intel-ic19.1u1-official-linux64_revA.html,
http://www.spec.org/cpu2017/flags/TyroneIT-Platform-Settings-V1-CLX-revA.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/Intel-ic19.1u1-official-linux64_revA.xml,
http://www.spec.org/cpu2017/flags/TyroneIT-Platform-Settings-V1-CLX-revA.xml.