clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking. Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking. Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on which high-level mode setting is passed, Flang will stop before doing a full link.
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking. Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking. Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on which high-level mode setting is passed, Flang will stop before doing a full link.
This macro indicates that the benchmark is being compiled on an AMD64-compatible system running the Linux operating system.
This macro specifies that the target system uses the LP64 data model; specifically, that integers are 32 bits, while longs and pointers are 64 bits.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This flag can be set for SPEC compilation for LINUX using default compiler.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This macro indicates that the benchmark is being compiled on an AMD64-compatible system running the Linux operating system.
This macro specifies that the target system uses the LP64 data model; specifically, that integers are 32 bits, while longs and pointers are 64 bits.
Specifies size of off_t data type.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This flag can be set for SPEC compilation for LINUX using default compiler.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
This option is used to indicate that the host system's integers are 32-bits wide, and longs and pointers are 64-bits wide. Not all benchmarks recognize this macro, but the preferred practice for data model selection applies the flags to all benchmarks; this flag description is a placeholder for those benchmarks that do not recognize this macro.
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64, x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target platform specified is 64-bit, otherwise the default is 32-bit.
Do not generate an error when linking multiple symbols of the same name.
Enables estimation of the virtual register pressure before performing loop invariant code motion. This estimation is used to decide the invariants that will be hoisted during loop invariant code motion.
Generate output files in LLVM formats suitable for link time optimization. When used with -S this generates LLVM intermediate language assembly files, otherwise this generates LLVM bitcode format object files (which may be passed to the linker depending on the stage selection options).
This flag enables vectorization of loops with complex control flow that can not be vectorized by loop and slp vectorizers.
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
Force the alignment of all blocks that have no fall-through predecessors (i.e. don't add nops that are executed). In log2 format (e.g 4 means align on 16B boundaries).
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is ignored even if set by the system headers.
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify -march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but which may not exist on earlier products.
Use the given vector functions library.
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least aggressive and 7 being the most aggressive level.
Possible values:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
Sets the limit at which loops will be unrolled. For example, if unroll threshold is set to 100 then only loops with 100 or fewer instructions will be unrolled.
Sets the compiler's inlining threshold level to the value passed as the argument. The inline threshold is used in the inliner heuristics to decide which functions should be inlined.
This option enables an optimization that transforms the data layout of a single dimensional array to provide better cache locality by analysing the access patterns.
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
This option enables an optimization that generates and calls specialized function versions when the loops inside function are vectorizable and the arguments are not aliased with each other. This optimization helps in function inlining and vectorization.
This option enables the GVN hoist pass, which is used to hoist computations from branches.
This option enables an optimization that does the slp vectorization across basic blocks. The SLP vectorizer vectorizes instructions within basic blocks. The global slp vectorizer analyzes instructions across basic blocks and vectorizes them.
Enables estimation of the virtual register pressure before performing loop invariant code motion. This estimation is used to decide the invariants that will be hoisted during loop invariant code motion.
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
Instructs the linker to use the first definition encountered for a symbol, and ignore all others.
Instructs the compiler to link with AMD-supported optimized math library.
Use the jemalloc library, which is a general purpose malloc(3) implementation that emphasizes fragmentation avoidance and scalable concurrency support.
Instructs the compiler to link with flang Fortran runtime libraries.
Instructs the compiler to link with flang Fortran runtime libraries.
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64, x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target platform specified is 64-bit, otherwise the default is 32-bit.
Selects the C++ language dialect.
Block Reordering
Possible values:
Generate output files in LLVM formats suitable for link time optimization. When used with -S this generates LLVM intermediate language assembly files, otherwise this generates LLVM bitcode format object files (which may be passed to the linker depending on the stage selection options).
This flag enables vectorization of loops with complex control flow that can not be vectorized by loop and slp vectorizers.
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
Force the alignment of all blocks that have no fall-through predecessors (i.e. don't add nops that are executed). In log2 format (e.g 4 means align on 16B boundaries).
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is ignored even if set by the system headers.
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify -march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but which may not exist on earlier products.
Use the given vector functions library.
This optimization does partial unswitching of loops where some part of the unswitched control flow remains in the loop.
Sets the limit at which loops will be unrolled. For example, if unroll threshold is set to 100 then only loops with 100 or fewer instructions will be unrolled.
Sets the compiler's inlining heuristics to an aggressive level by increasing the inline thresholds.
This option enables an optimization that generates and calls specialized function versions when the loops inside function are vectorizable and the arguments are not aliased with each other. This optimization helps in function inlining and vectorization.
Sets the limit at which loops will be unswitched. For example, if unswitch threshold is set to 100 then only loops with 100 or fewer instructions will be unswtched.
Run the loop rerolling pass.
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch) based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based on the number of times they are used within the loop. The heuristic can be controlled with the following options:
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least <n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n> where n is a positive integer and lower value of <n> facilitates more unswitching
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most <n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n> where n is a positive integer and higher value of <n> facilitates more unswitching
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer compilation times.
Run cleanup optimization passes after vectorization.
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
This option enables an optimization that does the slp vectorization across basic blocks. The SLP vectorizer vectorizes instructions within basic blocks. The global slp vectorizer analyzes instructions across basic blocks and vectorizes them.
Converts the call to floating point exponent version of pow to its integer exponent version if the floating-point exponent can be converted to integer. This option is set to true by default.
Instructs the linker to use the first definition encountered for a symbol, and ignore all others.
Block Reordering
Possible values:
Enables dead virtual function elimination optimization. Requires -flto=full.
Set the default symbol visibility for all global declarations.
Instructs the compiler to link with AMD-supported optimized math library.
Use the jemalloc library, which is a general purpose malloc(3) implementation that emphasizes fragmentation avoidance and scalable concurrency support.
Instructs the compiler to link with flang Fortran runtime libraries.
Instructs the compiler to link with flang Fortran runtime libraries.
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64, x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target platform specified is 64-bit, otherwise the default is 32-bit.
Enables inlining for recursive functions based on heuristics, with level 4 being most aggressive. Higher levels may lead to code bloat due to expansion of recursive functions at call sites.
Levels:
Enables loop strength reduction for nested loop structures. By default, the compiler will do loop strength reduction only for the innermost loop.
Enables splitting of long live ranges of loop induction variables which span loop boundaries. This helps reduce register pressure and can help avoid needless spills to memory and reloads from memory.
Generate output files in LLVM formats suitable for link time optimization. When used with -S this generates LLVM intermediate language assembly files, otherwise this generates LLVM bitcode format object files (which may be passed to the linker depending on the stage selection options).
This flag enables vectorization of loops with complex control flow that can not be vectorized by loop and slp vectorizers.
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
Force the alignment of all blocks that have no fall-through predecessors (i.e. don't add nops that are executed). In log2 format (e.g 4 means align on 16B boundaries).
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is ignored even if set by the system headers.
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify -march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but which may not exist on earlier products.
Use the given vector functions library.
Instructs the linker to use the first definition encountered for a symbol, and ignore all others.
Enables aggressive heuristics to get loop unrolling.
Sets the limit at which loops will be unrolled. For example, if unroll threshold is set to 100 then only loops with 100 or fewer instructions will be unrolled.
Instructs the compiler to link with AMD-supported optimized math library.
Use the jemalloc library, which is a general purpose malloc(3) implementation that emphasizes fragmentation avoidance and scalable concurrency support.
Instructs the compiler to link with flang Fortran runtime libraries.
Instructs the compiler to link with flang Fortran runtime libraries.
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64, x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target platform specified is 64-bit, otherwise the default is 32-bit.
Do not generate an error when linking multiple symbols of the same name.
Enables estimation of the virtual register pressure before performing loop invariant code motion. This estimation is used to decide the invariants that will be hoisted during loop invariant code motion.
Generate output files in LLVM formats suitable for link time optimization. When used with -S this generates LLVM intermediate language assembly files, otherwise this generates LLVM bitcode format object files (which may be passed to the linker depending on the stage selection options).
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
Force the alignment of all blocks that have no fall-through predecessors (i.e. don't add nops that are executed). In log2 format (e.g 4 means align on 16B boundaries).
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
Turns on LLVM's instrumenation based profiling.
Uses the profiling files generated from a program compiled with -fprofile-instr-generate to guide optimization decisions.
Enables all the optimizations from -O3 along with other aggressive optimizations that may violate strict compliance with language standards. Refer to the AOCC options document for the language you're using for more detailed documentation of optimizations enabled under -Ofast.
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify -march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but which may not exist on earlier products.
Use the given vector functions library.
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least aggressive and 7 being the most aggressive level.
Possible values:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
Sets the limit at which loops will be unrolled. For example, if unroll threshold is set to 100 then only loops with 100 or fewer instructions will be unrolled.
This option enables an optimization that transforms the data layout of a single dimensional array to provide better cache locality by analysing the access patterns.
This option enables an optimization that generates and calls specialized function versions when the loops inside function are vectorizable and the arguments are not aliased with each other. This optimization helps in function inlining and vectorization.
Sets the compiler's inlining threshold level to the value passed as the argument. The inline threshold is used in the inliner heuristics to decide which functions should be inlined.
This option enables the GVN hoist pass, which is used to hoist computations from branches.
This option enables an optimization that does the slp vectorization across basic blocks. The SLP vectorizer vectorizes instructions within basic blocks. The global slp vectorizer analyzes instructions across basic blocks and vectorizes them.
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
Enables estimation of the virtual register pressure before performing loop invariant code motion. This estimation is used to decide the invariants that will be hoisted during loop invariant code motion.
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
Instructs the compiler to link with AMD-supported optimized math library.
Use the jemalloc library, which is a general purpose malloc(3) implementation that emphasizes fragmentation avoidance and scalable concurrency support.
Generate code for a 32-bit environment. The 32-bit environment sets int, long and pointer to 32 bits and generates code that runs on any i386 system. The compiler generates x86 or IA32 32-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target platform specified is 64-bit, otherwise the default is 32-bit.
Do not generate an error when linking multiple symbols of the same name.
Enables estimation of the virtual register pressure before performing loop invariant code motion. This estimation is used to decide the invariants that will be hoisted during loop invariant code motion.
Generate output files in LLVM formats suitable for link time optimization. When used with -S this generates LLVM intermediate language assembly files, otherwise this generates LLVM bitcode format object files (which may be passed to the linker depending on the stage selection options).
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
Enables all the optimizations from -O3 along with other aggressive optimizations that may violate strict compliance with language standards. Refer to the AOCC options document for the language you're using for more detailed documentation of optimizations enabled under -Ofast.
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify -march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but which may not exist on earlier products.
Use the given vector functions library.
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least aggressive and 7 being the most aggressive level.
Possible values:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
Sets the limit at which loops will be unrolled. For example, if unroll threshold is set to 100 then only loops with 100 or fewer instructions will be unrolled.
This option enables an optimization that transforms the data layout of a single dimensional array to provide better cache locality by analysing the access patterns.
This option enables an optimization that generates and calls specialized function versions when the loops inside function are vectorizable and the arguments are not aliased with each other. This optimization helps in function inlining and vectorization.
Sets the compiler's inlining threshold level to the value passed as the argument. The inline threshold is used in the inliner heuristics to decide which functions should be inlined.
This option enables the GVN hoist pass, which is used to hoist computations from branches.
This option enables an optimization that does the slp vectorization across basic blocks. The SLP vectorizer vectorizes instructions within basic blocks. The global slp vectorizer analyzes instructions across basic blocks and vectorizes them.
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
Enables estimation of the virtual register pressure before performing loop invariant code motion. This estimation is used to decide the invariants that will be hoisted during loop invariant code motion.
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
In the 502/602.gcc benchmark description, "multiple definitions of symbols" is listed under the "Known Portability Issues" section, and this option is one of the suggested workarounds. This option causes Clang to revert to the same inlining behavior that GCC does when in pre-C99 mode.
Use the jemalloc library, which is a general purpose malloc(3) implementation that emphasizes fragmentation avoidance and scalable concurrency support.
Generate code for a 32-bit environment. The 32-bit environment sets int, long and pointer to 32 bits and generates code that runs on any i386 system. The compiler generates x86 or IA32 32-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target platform specified is 64-bit, otherwise the default is 32-bit.
Block Reordering
Possible values:
Generate output files in LLVM formats suitable for link time optimization. When used with -S this generates LLVM intermediate language assembly files, otherwise this generates LLVM bitcode format object files (which may be passed to the linker depending on the stage selection options).
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
Force the alignment of all blocks that have no fall-through predecessors (i.e. don't add nops that are executed). In log2 format (e.g 4 means align on 16B boundaries).
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
Enables all the optimizations from -O3 along with other aggressive optimizations that may violate strict compliance with language standards. Refer to the AOCC options document for the language you're using for more detailed documentation of optimizations enabled under -Ofast.
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify -march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but which may not exist on earlier products.
Use the given vector functions library.
Sets the compiler's inlining heuristics to an aggressive level by increasing the inline thresholds.
Sets the limit at which loops will be unrolled. For example, if unroll threshold is set to 100 then only loops with 100 or fewer instructions will be unrolled.
This option enables an optimization that generates and calls specialized function versions when the loops inside function are vectorizable and the arguments are not aliased with each other. This optimization helps in function inlining and vectorization.
Enables estimation of the virtual register pressure before performing loop invariant code motion. This estimation is used to decide the invariants that will be hoisted during loop invariant code motion.
Run the loop rerolling pass.
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch) based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based on the number of times they are used within the loop. The heuristic can be controlled with the following options:
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least <n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n> where n is a positive integer and lower value of <n> facilitates more unswitching
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most <n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n> where n is a positive integer and higher value of <n> facilitates more unswitching
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer compilation times.
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
This option enables an optimization that does the slp vectorization across basic blocks. The SLP vectorizer vectorizes instructions within basic blocks. The global slp vectorizer analyzes instructions across basic blocks and vectorizes them.
Block Reordering
Possible values:
Enables dead virtual function elimination optimization. Requires -flto=full.
Set the default symbol visibility for all global declarations.
Use the jemalloc library, which is a general purpose malloc(3) implementation that emphasizes fragmentation avoidance and scalable concurrency support.
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64, x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target platform specified is 64-bit, otherwise the default is 32-bit.
Selects the C++ language dialect.
Block Reordering
Possible values:
Generate output files in LLVM formats suitable for link time optimization. When used with -S this generates LLVM intermediate language assembly files, otherwise this generates LLVM bitcode format object files (which may be passed to the linker depending on the stage selection options).
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
Force the alignment of all blocks that have no fall-through predecessors (i.e. don't add nops that are executed). In log2 format (e.g 4 means align on 16B boundaries).
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
Enables all the optimizations from -O3 along with other aggressive optimizations that may violate strict compliance with language standards. Refer to the AOCC options document for the language you're using for more detailed documentation of optimizations enabled under -Ofast.
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify -march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but which may not exist on earlier products.
Use the given vector functions library.
Sets the compiler's inlining heuristics to an aggressive level by increasing the inline thresholds.
Sets the limit at which loops will be unrolled. For example, if unroll threshold is set to 100 then only loops with 100 or fewer instructions will be unrolled.
This option enables an optimization that generates and calls specialized function versions when the loops inside function are vectorizable and the arguments are not aliased with each other. This optimization helps in function inlining and vectorization.
Enables estimation of the virtual register pressure before performing loop invariant code motion. This estimation is used to decide the invariants that will be hoisted during loop invariant code motion.
Run the loop rerolling pass.
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch) based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based on the number of times they are used within the loop. The heuristic can be controlled with the following options:
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least <n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n> where n is a positive integer and lower value of <n> facilitates more unswitching
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most <n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n> where n is a positive integer and higher value of <n> facilitates more unswitching
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer compilation times.
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
This option enables an optimization that does the slp vectorization across basic blocks. The SLP vectorizer vectorizes instructions within basic blocks. The global slp vectorizer analyzes instructions across basic blocks and vectorizes them.
Block Reordering
Possible values:
Enables dead virtual function elimination optimization. Requires -flto=full.
Set the default symbol visibility for all global declarations.
Instructs the compiler to link with AMD-supported optimized math library.
Use the jemalloc library, which is a general purpose malloc(3) implementation that emphasizes fragmentation avoidance and scalable concurrency support.
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64, x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target platform specified is 64-bit, otherwise the default is 32-bit.
Enables inlining for recursive functions based on heuristics, with level 4 being most aggressive. Higher levels may lead to code bloat due to expansion of recursive functions at call sites.
Levels:
Enables loop strength reduction for nested loop structures. By default, the compiler will do loop strength reduction only for the innermost loop.
Enables splitting of long live ranges of loop induction variables which span loop boundaries. This helps reduce register pressure and can help avoid needless spills to memory and reloads from memory.
Generate output files in LLVM formats suitable for link time optimization. When used with -S this generates LLVM intermediate language assembly files, otherwise this generates LLVM bitcode format object files (which may be passed to the linker depending on the stage selection options).
This option enables an optimization that generates and calls specialized function versions when they are called with constant arguments. This optimization helps in function inlining.
Force the alignment of all blocks that have no fall-through predecessors (i.e. don't add nops that are executed). In log2 format (e.g 4 means align on 16B boundaries).
This option eliminates the array computations based on their usage. The computations on unused array elements and computations on zero valued array elements are eliminated with this optimization. -flto as whole program analysis is required to perform this optimization.
Possible values:
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is ignored even if set by the system headers.
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify -march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but which may not exist on earlier products.
Use the given vector functions library.
Enables aggressive heuristics to get loop unrolling.
Sets the limit at which loops will be unrolled. For example, if unroll threshold is set to 100 then only loops with 100 or fewer instructions will be unrolled.
Instructs the compiler to link with AMD-supported optimized math library.
Use the jemalloc library, which is a general purpose malloc(3) implementation that emphasizes fragmentation avoidance and scalable concurrency support.
Instructs the compiler to link with flang Fortran runtime libraries.
Instructs the compiler to link with flang Fortran runtime libraries.
Do not warn about unused command line arguments.
Do not warn about unused command line arguments.
Do not warn about unused command line arguments.
Specifies a directory to search for libraries. Use -L to add directories to the search path for library files. Multiple -L options are valid. However, the position of multiple -L options is important relative to -l options supplied.
Do not warn about unused command line arguments.
Specifies a directory to search for libraries. Use -L to add directories to the search path for library files. Multiple -L options are valid. However, the position of multiple -L options is important relative to -l options supplied.
Do not warn about unused command line arguments.
Specifies a directory to search for libraries. Use -L to add directories to the search path for library files. Multiple -L options are valid. However, the position of multiple -L options is important relative to -l options supplied.
Do not warn about unused command line arguments.
Specifies a directory to search for libraries. Use -L to add directories to the search path for library files. Multiple -L options are valid. However, the position of multiple -L options is important relative to -l options supplied.
This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.
Somewhere between -O0 and -O2.
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
This optimization does partial unswitching of loops where some part of the unswitched control flow remains in the loop.
Using numactl
to bind processes and memory to cores
For multi-copy runs or single copy runs on systems with multiple sockets, it is advantageous to bind a process to a
particular core. Otherwise, the OS may arbitrarily move your process from one core to another. This can affect
performance. To help, SPEC allows the use of a "submit" command where users can specify a utility to use to bind
processes. We have found the utility 'numactl
' to be the best choice.
numactl
runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a
command and inherited by all of its children. The numactl
flag "--physcpubind
" specifies
which core(s) to bind the process. "-l
" instructs numactl
to keep a process's memory on the
local node while "-m
" specifies which node(s) to place a process's memory. For full details on using
numactl
, please refer to your Linux documentation, 'man numactl
'
Note that some older versions of numactl
incorrectly interpret application arguments as its own. For
example, with the command "numactl --physcpubind=0 -l a.out -m a
", numactl
will interpret
a.out
's "-m
" option as its own "-m
" option. To work around this problem, we put
the command to be run in a shell script and then run the shell script using numactl
. For example:
"echo 'a.out -m a' > run.sh ; numactl --physcpubind=0 bash run.sh
"
Transparent Huge Pages (THP)
THP is an abstraction layer that automates most aspects of creating, managing, and using huge pages. THP is designed to hide much of the complexity in using huge pages from system administrators and developers, as normal huge pages must be assigned at boot time, can be difficult to manage manually, and often require significant changes to code in order to be used effectively. Most recent Linux OS releases have THP enabled by default.
ulimit -s <n>
Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.
ulimit -l <n>
Sets the maximum size of memory that may be locked into physical memory.
powersave -f
(on SuSE)
Makes the powersave daemon set the CPUs to the highest supported frequency.
/etc/init.d/cpuspeed stop
(on Red Hat)
Disables the cpu frequency scaling program in order to set the CPUs to the highest supported frequency.
LD_LIBRARY_PATH
An environment variable that indicates the location in the filesystem of bundled libraries to use when running the benchmark binaries.
kernel/randomize_va_space
This option can be used to select the type of process address space randomization that is used in the system, for architectures that support this feature.
norandmaps
" parameter.CONFIG_COMPAT_BRK
option is enabled.CONFIG_COMPAT_BRK
is
disabled.MALLOC_CONF
An environment variable set to tune the jemalloc allocation strategy during the execution of the binaries. This environment variable setting is not needed when building the binaries on the system under test.
PGHPF_ZMEM
An environment variable used to initialize the allocated memory. Setting PGHPF_ZMEM to "Yes" has the effect of initializing all allocated memory to zero.
GOMP_CPU_AFFINITY
This environment variable is used to set the thread affinity for threads spawned by OpenMP.
OMP_DYNAMIC
This environment variable is defined as part of the OpenMP standard. Setting it to "false" prevents the OpenMP runtime from dynamically adjusting the number of threads to use for parallel execution.
For more information, see chapter 4 ("Environment Variables") in the OpenMP 4.5 Specification.
OMP_SCHEDULE
This environment variable is defined as part of the OpenMP standard. Setting it to "static" causes loop iterations to be assigned to threads in round-robin fashion in the order of the thread number.
For more information, see chapter 4 ("Environment Variables") in the OpenMP 4.5 Specification.
OMP_STACKSIZE
This environment variable is defined as part of the OpenMP standard and controls the size of the stack for threads created by OpenMP.
For more information, see chapter 4 ("Environment Variables") in the OpenMP 4.5 Specification.
OMP_THREAD_LIMIT
This environment variable is defined as part of the OpenMP standard and limits the maximum number of OpenMP threads that can be created.
For more information, see chapter 4 ("Environment Variables") in the OpenMP 4.5 Specification.
C States:
C States allow the processor to enter lower power states when idle. When set to Enabled (OS controlled) or when set to Autonomous (if Hardware controlled is supported), the processor can operate in all available Power States to save power, but my increase memory latency and frequency jitter.
L3 cache as NUMA Domain:
This field specifies that each CCX within the processor will be declared as a NUMA Domain.
Dram Refresh Delay:
By enabling CPU memory controller to delay running the REFRESH commands, you can improve the performance for some workloads. By minimizing the delay time, it is ensured that the memory controller runs the REFRESH command at regular intervals. For Intel-based servers, this setting only affects systems configured with DIMMs which use 8Gb density DRAMs.
L1 Stream HW prefetcher, L2 Stream HW prefetcher:
Most workloads will benefit from the L1 and L2 Stream Hardware prefetchers gathering data and keeping the core pipeline busy. There are however some workloads that are very random in nature and will actually obtain better overall performance by disabling one or both of the prefetchers.
UPI Prefetch:
Enables you to get the memory read started early on DDR bus. The Ultra Path Interconnect (UPI) Rx path will spawn the speculative memory read to Integrated Memory Controller (iMC) directly.
Dynamic Link Width Management (DLWM):
DLWM reduces the XGMI link width between sockets from x16 to x8 (default), when no traffic is detected on the link. This feature is optimized to trade power between core and high IO/memory bandwidth workloads.
Forced = Force link width to x16, x8, or x2.
LLC Prefetch:
This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit (DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance. Disabled: Disables the LLC prefetcher. Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.
Dead Line LLC Alloc:
In the Skylake cache scheme, mid-level cache (MLC) evictions are filled into the last level cache (LLC). If a line is evicted from the MLC to the LLC, the Skylake core can flag the evicted MLC lines as "dead". This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if the option is disabled. Disabled: Disabling this option can save space in the LLC by never filling dead lines into the LLC. Enabled: Opportunistically fill dead lines in LLC, if space is available.
Directory AtoS:
AtoS optimization reduces remote read latencies for repeat read accesses without intervening writes.
Algorithm performance Boost Disable (ApbDis):
When enabled a specific hard-fused Data Fabric (SOC) p-state is forced for optimizing workloads sensitive to latency or throughput. When disabled P-states will be automatically managed by the Application Power Management, allowing the processor to provide maximum performance while remaining within a specified power-delivery and thermal envelope.
Fan Speed:
Selecting this option allows additional cooling to the server. In case hardware is added (example, new PCIe cards), it may require additional cooling. A fan speed offset causes fan speeds to increase (by the offset % value) over baseline fan speeds calculated by the Thermal Control algorithm. Maximum — Drives fan speeds to full speed.
Determinism Slider:
It controls whether BIOS will enable determinism to control performance. Performance: BIOS will enable 100% deterministic performance control. Power: BIOS will not enable deterministic performance control.
CPU Power Management set to Maximum Performance:
Allows selection of CPU power management methodology. Maximum Performance is typically selected for performance-centric workloads where it is acceptable to consume additional power to achieve the highest possible performance for the computing environment. This mode drives processor frequency to the maximum across all cores (although idled cores can still be frequency reduced by C-state enforcement through BIOS or OS mechanisms if enabled). This mode also offers the lowest latency of the CPU Power Management Mode options, so is always preferred for latency-sensitive environments. OS DBPM is another performance-per-watt option that relies on the operating system to dynamically control individual cores in order to save power.
Memory Frequency set to Maximum Performance:
Governs the BIOS memory frequency. The variables that govern maximum memory frequency include the maximum rated frequency of the DIMMs, the DIMMs per channel population, the processor choice, and this BIOS option. Additional power savings can be achieved by reducing the memory frequency, at the expense of reduced performance. Read-only unless System Profile is set to Custom.
Efficiency Optimized Mode Disabled:
This field enables/disabled Efficiency Optimized Mode. Efficiency Optimized Mode maximizes Performance-per-Watt by opportunistically reducing frequency/power.
NUMA Nodes Per Socket:
NUMA nodes per socket (NPS) field allows you to configure the memory NUMA domains per socket. The configuration can consist of one whole domain (NPS1), two domains (NPS2), or four domains (NPS4). In the case of a two-socket platform, an additional NPS profile is available to have whole system memory to be mapped as single NUMA domain (NPS0).
CCX as NUMA Domain:
In addition to selecting the number of NUMA domains via NPS option, the processor allows for making memory per CCX as NUMA domain. In the processor each CCD has a maximum of two CCXs with each CCX having a shared last-level cache (LLC, or L3 cache) for all cores. The CCX as NUMA domain option allows for each LLC to be configured as a NUMA domain so that for certain workloads pinning execution to a single NUMA domain can be done.
Adaptive Double DRAM Device Correction (ADDDC):
When Adaptive Double DRAM Device Correction (ADDDC) is enabled, failing DRAM’s are dynamically mapped out. When set to enabled, it can have some impact to system performance under certain workloads. This feature is applicable for x4 DIMMs only.
DCU Streamer Prefetcher:
Enables or disables Data Cache Unit (DCU) Streamer Prefetcher. This setting can affect performance, depending on the application running on the server. DCU streamer prefetchers detect multiple reads to a single cache line in a certain period of time and choose to load the following cache line to the L1 data caches. Recommended for High Performance Computing applications.
DCU IP Prefetcher:
Enables or disables Data Cache Unit (DCU) IP Prefetcher. DCU IP Prefetcher looks for sequential load history to determine whether to prefetch the data to the L1 caches.
Memory Frequency:
Governs the BIOS memory frequency. The variables that govern maximum memory frequency include the maximum rated frequency of the DIMMs, the DIMMs per channel population, the processor choice, and this BIOS option. Additional power savings can be achieved by reducing the memory frequency, at the expense of reduced performance.
Turbo Boost:
Governs the Boost Technology. This feature allows the processor cores to be automatically clocked up in frequency beyond the advertised processor speed. The amount of increased frequency (or 'turbo upside') one can expect from an EPYC processor depends on the fewer cores being exercised with work the higher the potential turbo upside. The potential drawback for Boost are mainly centered on increased power consumption and possible frequency jitter that can affect a small minority of latency-sensitive environments.
C1E:
When set to Enabled, the processor is allowed to switch to minimum performance state when idle.
CPU Interconnect Bus Link Power Management:
When Enabled, CPU interconnect bus link power management can reduce overall system power a bit while slightly reducing system performance.
CPU Performance:
Maximum Performance is typically selected for performance-centric workloads where it is acceptable to consume additional power to achieve the highest possible performance for the computing environment. This mode drives processor frequency to the maximum across all cores (although idled cores can still be frequency reduced by C-state enforcement through BIOS or OS mechanisms if enabled). This mode also offers the lowest latency of the CPU Power Management Mode options, so is always preferred.
Energy Efficient Policy:
The CPU uses the setting to manipulate the internal behavior of the processor and determines
whether to target higher performance or better power savings. The possible settings are: Performance, Balanced Performance, Balanced Energy, Energy Efficient.
Energy Efficient Turbo:
Permits Energy Efficient Turbo to be Enabled or Disabled.
Energy Efficient Turbo (EET) is a mode of operation where a processor's core frequency is adjusted within the turbo range based on workload.
Logical Processor:
Each processor core supports up to two logical processors. When set to Enabled, the BIOS reports all logical processors. When set to Disabled, the BIOS only reports one logical processor per core. Generally, higher processor count results in increased performance for most multi-threaded workloads and the recommendation is to keep this enabled. However, there are some floating point/scientific workloads, including HPC workloads, where disabling this feature may result in higher performance.
Memory Patrol Scrub:
Patrol Scrubbing searches the memory for errors and repairs correctable errors to prevent the accumulation of memory errors. When set to Disabled, no patrol scrubbing will occur. When set to Standard Mode, the entire memory array will be scrubbed once in a 24 hour period. When set to Extended Mode, the entire memory array will be scrubbed more frequently to further increase system reliability.
Memory Refresh Rate:
The memory controller will periodically refresh the data in memory. The frequency at which memory is normally refreshed is referred to as 1X refresh rate. When memory modules are operating at a higher than normal temperature or to further increase system reliability, the refresh rate can be set to 2X, but may have a negative impact on memory subsystem performance under some circumstances.
PCI ASPM L1 Link Power Management:
When Enabled, PCIe Advanced State Power Management (ASPM) can reduce overall system power
a bit while slightly reducing system performance.
NOTE: Some devices may not perform properly (they may hang or cause the system to hang)
when ASPM is enabled, for this reason L1 will only be enabled for validated qualified cards.
System Profile:
When set to Custom, you can change setting of each option. Under Custom mode when C States is enabled, Monitor/Mwait should also be Enabled.
Monitor/Mwait:
Specifies whether Monitor/Mwait instructions are enabled. Monitor/Mwait is only active when C States is set to Disabled.
Sub NUMA Cluster:
When Enabled, Sub NUMA Clustering (SNC) is a feature for breaking up the LLC into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. It improves average latency to the LLC.
Uncore Frequency:
Selects the Processor Uncore Frequency.
Dynamic mode allows processor to optimize power resources across the cores and uncore during runtime.
The optimization of the uncore frequency to either save power or optimize performance is influenced
by the setting of the Energy Efficient Policy.
Virtualization Technology:
When set to Enabled, the BIOS will enable processor Virtualization features and provide the virtualization support to the Operating System (OS) through the DMAR table. In general, only virtualized environments such as VMware(r) ESX (tm), Microsoft Hyper-V(r) , Red Hat(r) KVM, and other virtualized operating systems will take advantage of these features. Disabling this feature is not known to significantly alter the performance or power characteristics of the system, so leaving this option Enabled is advised for most cases.
nohz_full:
This kernel option sets adaptive tick mode (NOHZ_FULL) to specified processors. Since the number of interrupts is reduced to ones per second, latency-sensitive applications can take advantage of it.
Memory Interleaving:
When Enabled, memory interleaving is supported if a symmetric memory configuration is installed. When set to Disabled, the system supports Non-Uniform Memory Access (NUMA) (asymmetric) memory configurations. Channel interleaving is available with all configurations and is the intra-die memory interleave option. With channel interleaving the memory behind each UMC will be interleaved and seen as 1 NUMA domain per die.
Flag description origin markings:
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2021 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.1.5.
Report generated on 2021-03-30 15:32:51 by SPEC CPU2017 flags formatter v5178.