CPU2017 Flag Description
GIGA-BYTE TECHNOLOGY CO., LTD. R272-Z30 (AMD EPYC 7773X, 2.20GHz)
Compilers: AMD Optimizing C/C++ Compiler Suite
Base Compiler Invocation
-
- clang
![[user]](https://www.spec.org/auto/cpu2017/images/user.png)
- CC, LD
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang++
- CXX, LD
-
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- flang
- FC, LD
-
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on
which high-level mode setting is passed, Flang will stop before doing a full link.
-
- flang
- FC, LD
-
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on
which high-level mode setting is passed, Flang will stop before doing a full link.
-
- clang
- CC
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang++
- CXX, LD
-
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang
- CC
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang++
- CXX, LD
-
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang
- CC
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- flang
- FC
-
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on
which high-level mode setting is passed, Flang will stop before doing a full link.
Peak Compiler Invocation
-
- clang
- CC, LD
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang++
- CXX, LD
-
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- flang
- FC, LD
-
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on
which high-level mode setting is passed, Flang will stop before doing a full link.
-
- flang
- FC, LD
-
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on
which high-level mode setting is passed, Flang will stop before doing a full link.
-
- clang
- CC
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang++
- CXX, LD
-
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang
- CC
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang++
- CXX, LD
-
clang++ C++ compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- clang
- CC
-
clang is a C compiler which encompasses preprocessing, parsing, optimization, code generation, assembly, and linking.
Depending on which high-level mode setting is passed, Clang will stop before doing a full link.
-
- flang
- FC
-
flang is a Fortran compiler which encompasses parsing, optimization, code generation, assembly, and linking. Depending on
which high-level mode setting is passed, Flang will stop before doing a full link.
Base Portability Flags
-
![[suite]](https://www.spec.org/auto/cpu2017/images/suite.png)
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
-
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
-
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
Peak Portability Flags
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
-
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
-
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
-
- EXTRA_PORTABILITY
-
This option is used to indicate that the host system's integers are 32-bits
wide, and longs and pointers are 64-bits wide. Not all benchmarks
recognize this macro, but the preferred practice for data model selection
applies the flags to all benchmarks; this flag description is a placeholder
for those benchmarks that do not recognize this macro.
Base Optimization Flags
-
- -m64
- CC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
- -Wl,-mllvm -Wl,-enable-loop-fusion
- EXTRA_LDFLAGS
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
- -O3
- COPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver3
- COPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- COPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -fstruct-layout=5
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
- -mllvm -enable-loop-fusion
- COPTIMIZE
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
-
-
-
-
- -m64
- CXX, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
-
-
- -Wl,-mllvm -Wl,-enable-loop-fusion
- EXTRA_LDFLAGS
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
- -O3
- CXXOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver3
- CXXOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- CXXOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
-
-
-
-
-
-
- -mllvm -aggressive-loop-unswitch
- CXXOPTIMIZE
-
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch)
based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be
minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based
on the number of times they are used within the loop. The heuristic can be controlled with the following options:
- -unswitch-identical-branches-min-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n>
where n is a positive integer and lower value of <n> facilitates more unswitching.
- -unswitch-identical-branches-max-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n>
where n is a positive integer and higher value of <n> facilitates more unswitching.
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads
to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer
compilation times.
- Includes:
-
-
-
-
-
- -mllvm -enable-loop-fusion
- CXXOPTIMIZE
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
-
-
-
-
- -m64
- FC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -Wl,-mllvm -Wl,-enable-loop-fusion
- EXTRA_LDFLAGS
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
-
- -O3
- FOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver3
- FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
-
- -Mrecursive
- FOPTIMIZE
-
Allocate local variables on the stack, thus allowing recursion.
SAVEd, data-initialized, or namelist members are always allocated
statically, regardless of the setting of this switch.
-
-
-
-
-
-
-
-
- -mllvm -enable-loop-fusion
- FOPTIMIZE
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
- -mllvm -enable-loopinterchange
- FOPTIMIZE
-
This option enables the classical loop interchange or loop permutation transformation on a loop nest.
This transformation reorders the loops in a multi-dimensional loop nest, checking for various legality criteria in the
process. The goal is to find a reordering of the loops such that the number of loop invariant expressions that may be
hoisted out from an inner loop to a loop at a higher level is maximized.
This transformation is off by default and may be enabled by using this option.
-
- -mllvm -compute-interchange-order
- FOPTIMIZE
-
When loop interchange is enabled, this option enables the heuristic which determines the best reordering of the loops in a
multi-dimensional loop nest such that the number of invariant expressions that may be hoisted out from an inner level loop
to an outer one is maximized. This option is off by default.
-
-
-
-
-
- -m64
- CC, FC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -Wl,-mllvm -Wl,-enable-loop-fusion
- EXTRA_LDFLAGS
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
- -O3
- COPTIMIZE, FOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver3
- COPTIMIZE, FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- COPTIMIZE, FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -fstruct-layout=5
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
- -mllvm -enable-loop-fusion
- COPTIMIZE, FOPTIMIZE
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
-
-
- -Mrecursive
- FOPTIMIZE
-
Allocate local variables on the stack, thus allowing recursion.
SAVEd, data-initialized, or namelist members are always allocated
statically, regardless of the setting of this switch.
-
-
-
-
-
- -mllvm -enable-loopinterchange
- FOPTIMIZE
-
This option enables the classical loop interchange or loop permutation transformation on a loop nest.
This transformation reorders the loops in a multi-dimensional loop nest, checking for various legality criteria in the
process. The goal is to find a reordering of the loops such that the number of loop invariant expressions that may be
hoisted out from an inner loop to a loop at a higher level is maximized.
This transformation is off by default and may be enabled by using this option.
-
- -mllvm -compute-interchange-order
- FOPTIMIZE
-
When loop interchange is enabled, this option enables the heuristic which determines the best reordering of the loops in a
multi-dimensional loop nest such that the number of invariant expressions that may be hoisted out from an inner level loop
to an outer one is maximized. This option is off by default.
-
-
-
-
-
- -m64
- CC, CXX, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
-
-
- -Wl,-mllvm -Wl,-enable-loop-fusion
- EXTRA_LDFLAGS
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
- -O3
- COPTIMIZE, CXXOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver3
- COPTIMIZE, CXXOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- COPTIMIZE, CXXOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -fstruct-layout=5
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
- -mllvm -enable-loop-fusion
- COPTIMIZE, CXXOPTIMIZE
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
-
-
-
-
-
- -mllvm -aggressive-loop-unswitch
- CXXOPTIMIZE
-
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch)
based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be
minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based
on the number of times they are used within the loop. The heuristic can be controlled with the following options:
- -unswitch-identical-branches-min-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n>
where n is a positive integer and lower value of <n> facilitates more unswitching.
- -unswitch-identical-branches-max-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n>
where n is a positive integer and higher value of <n> facilitates more unswitching.
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads
to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer
compilation times.
- Includes:
-
-
-
-
-
-
-
- -m64
- CC, CXX, FC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
-
-
- -Wl,-mllvm -Wl,-enable-loop-fusion
- EXTRA_LDFLAGS
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
- -O3
- COPTIMIZE, CXXOPTIMIZE, FOPTIMIZE
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -march=znver3
- COPTIMIZE, CXXOPTIMIZE, FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- COPTIMIZE, CXXOPTIMIZE, FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -fstruct-layout=5
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
- -mllvm -enable-loop-fusion
- COPTIMIZE, CXXOPTIMIZE, FOPTIMIZE
-
This option enables the classical loop fusion transformation where the bodies of multiple loop nests are fused into one
loop nest. The transformation checks various legality criteria involving the bounds of the loop nests involved, the control
flow nesting of the loop nests and so on.
Loop fusion enables reuse of memory access operations across the loop nests and is also beneficial for cache performance.
As part of the profitability check for this transformation it uses code size thresholds which control the size of the fused
loop body created.
This transformation is off by default and may be enabled by using this option.
-
-
-
-
-
-
- -mllvm -aggressive-loop-unswitch
- CXXOPTIMIZE
-
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch)
based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be
minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based
on the number of times they are used within the loop. The heuristic can be controlled with the following options:
- -unswitch-identical-branches-min-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n>
where n is a positive integer and lower value of <n> facilitates more unswitching.
- -unswitch-identical-branches-max-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n>
where n is a positive integer and higher value of <n> facilitates more unswitching.
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads
to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer
compilation times.
- Includes:
-
-
-
-
-
- -Mrecursive
- FOPTIMIZE
-
Allocate local variables on the stack, thus allowing recursion.
SAVEd, data-initialized, or namelist members are always allocated
statically, regardless of the setting of this switch.
-
-
-
-
- -mllvm -enable-loopinterchange
- FOPTIMIZE
-
This option enables the classical loop interchange or loop permutation transformation on a loop nest.
This transformation reorders the loops in a multi-dimensional loop nest, checking for various legality criteria in the
process. The goal is to find a reordering of the loops such that the number of loop invariant expressions that may be
hoisted out from an inner loop to a loop at a higher level is maximized.
This transformation is off by default and may be enabled by using this option.
-
- -mllvm -compute-interchange-order
- FOPTIMIZE
-
When loop interchange is enabled, this option enables the heuristic which determines the best reordering of the loops in a
multi-dimensional loop nest such that the number of invariant expressions that may be hoisted out from an inner level loop
to an outer one is maximized. This option is off by default.
-
-
-
-
Peak Optimization Flags
-
- -m64
- CC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
- -march=znver3
- COPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- COPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -fstruct-layout=7
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
-
-
- -m64
- CXX, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
-
-
-
- -march=znver3
- CXXOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- CXXOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
-
-
-
-
-
- -mllvm -aggressive-loop-unswitch
- CXXOPTIMIZE
-
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch)
based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be
minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based
on the number of times they are used within the loop. The heuristic can be controlled with the following options:
- -unswitch-identical-branches-min-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n>
where n is a positive integer and lower value of <n> facilitates more unswitching.
- -unswitch-identical-branches-max-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n>
where n is a positive integer and higher value of <n> facilitates more unswitching.
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads
to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer
compilation times.
- Includes:
-
-
-
-
-
- -m64
- FC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -march=znver3
- FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -Mrecursive
- FOPTIMIZE
-
Allocate local variables on the stack, thus allowing recursion.
SAVEd, data-initialized, or namelist members are always allocated
statically, regardless of the setting of this switch.
-
-
-
-
-
-
-
- -m64
- FC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -march=znver3
- FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
-
- -Mrecursive
- FOPTIMIZE
-
Allocate local variables on the stack, thus allowing recursion.
SAVEd, data-initialized, or namelist members are always allocated
statically, regardless of the setting of this switch.
-
-
-
-
-
-
-
- -m64
- FC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -march=znver3
- FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -Mrecursive
- FOPTIMIZE
-
Allocate local variables on the stack, thus allowing recursion.
SAVEd, data-initialized, or namelist members are always allocated
statically, regardless of the setting of this switch.
-
-
-
-
-
-
-
-
-
- -m64
- CC, FC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
- -march=znver3
- COPTIMIZE, FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- COPTIMIZE, FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -fstruct-layout=7
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
- -Mrecursive
- FOPTIMIZE
-
Allocate local variables on the stack, thus allowing recursion.
SAVEd, data-initialized, or namelist members are always allocated
statically, regardless of the setting of this switch.
-
-
-
-
- -m64
- CC, CXX, FC, LD
-
Generate code for a 64-bit environment. The 64-bit environment sets int to 32 bits and long and
pointer to 64 bits and generates code for AMD's x86-64 architecture. The compiler generates AMD64, INTEL64,
x86-64 64-bit ABI. The default on a 32-bit host is 32-bit ABI. The default on a 64-bit host is 64-bit ABI if the target
platform specified is 64-bit, otherwise the default is 32-bit.
-
-
-
-
-
-
-
-
-
-
-
- -march=znver3
- COPTIMIZE, CXXOPTIMIZE, FOPTIMIZE
-
Specify that Clang should generate code for a specific processor family member and later. For example, if you specify
-march=znver1, the compiler is allowed to generate instructions that are valid on AMD Zen processors, but
which may not exist on earlier products.
-
-
- -ffast-math
- COPTIMIZE, CXXOPTIMIZE, FOPTIMIZE
-
Enables a range of optimizations that provide faster, though sometimes less precise, mathematical operations that may
not conform to the IEEE-754 specifications. When this option is specified, the __STDC_IEC_559__ macro is
ignored even if set by the system headers.
-
- -fstruct-layout=7
- COPTIMIZE
-
Analyzes the whole program to determine if the structures in the code can be peeled and if pointer or integer fields in
the structure can be compressed. If feasible, this optimization transforms the code to enable these improvements. This
transformation is likely to improve cache utilization and memory bandwidth. This, in turn, is expected to improve the
scalability of programs executed on multiple cores.
This is effective only under -flto as whole program analysis is required to perform this optimization. You can choose
different levels of aggressiveness with which this optimization can be applied to your application with 1 being the least
aggressive and 7 being the most aggressive level.
Possible values:
- fstruct-layout=1: enables structure peeling.
- fstruct-layout=2: enables structure peeling and selectively compresses self-referential pointers in these
structures to 32-bit pointers wherever safe.
- fstruct-layout=3: enables structure peeling and selectively compresses self-referential pointers in these
structures to 16-bit pointers wherever safe.
- fstruct-layout=4: enables structure peeling, pointer compression as in level 2 and further enables
compression of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=5: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of integer type. This is performed under a strict safety check.
- fstruct-layout=6: enables structure peeling, pointer compression as in level 2 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' fields are in
range 0 to +(2^31 - 1), otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
- fstruct-layout=7: enables structure peeling, pointer compression as in level 3 and further enables compression
of structure fields which are of type 64-bit 'signed int' or 'unsigned Int'. The user needs to ensure that the values
assigned to 64-bit 'signed int' fields are in range -(2^31 - 1) to +(2^31 - 1) and 64-bit 'unsigned int' field are in
range 0 to +(2^31 - 1) , otherwise, incorrect results may be obtained. This compression is performed without considering
any safety analysis and so the user needs to ensure the safety based on the program compiled.
Note:
fstruct-layout=4 and fstruct-layout=5 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of safe compression of integer fields in structures. Going from fstruct-layout=4 to fstruct-layout=5 may result
in higher performance if the pointer values are such that the pointers can be compressed to 16-bits.
fstruct-layout=6 and fstruct-layout=7 are derived from fstruct-layout=2 and fstruct-layout=3 respectively with the added
feature of compression of integer fields in structures. These are similar to fstruct-layout=4 and fstruct-layout=5, but
here, the integer fields of the structures are always compressed from 64-bits to 32-bits without any safety guarantee.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- -mllvm -aggressive-loop-unswitch
- CXXOPTIMIZE
-
This option enables aggressive loop unswitching heuristic (including -enable-partial-unswitch)
based on the usage of the branch conditional values. Loop unswitching leads to code-bloat. Code-bloat can be
minimized if the hoisted condition is executed more often. This heuristic prioritizes the conditions based
on the number of times they are used within the loop. The heuristic can be controlled with the following options:
- -unswitch-identical-branches-min-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at least
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 3.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-min-count=<n>
where n is a positive integer and lower value of <n> facilitates more unswitching.
- -unswitch-identical-branches-max-count=<n>
Enables unswitching of a loop with respect to a branch conditional value (B), where B appears in at most
<n> compares in the loop. This option is enabled with -aggressive-loop-unswitch. Default value is 6.
Usage: -mllvm -aggressive-loop-unswitch -mllvm -unswitch-identical-branches-max-count=<n>
where n is a positive integer and higher value of <n> facilitates more unswitching.
Note: These options may facilitate more unswitching in some of the workloads. Since loop-unswitching inherently leads
to code bloat, facilitating more unswitching may significantly increase the code size and hence may also lead to longer
compilation times.
- Includes:
-
-
-
- -Mrecursive
- FOPTIMIZE
-
Allocate local variables on the stack, thus allowing recursion.
SAVEd, data-initialized, or namelist members are always allocated
statically, regardless of the setting of this switch.
-
-
-
Implicitly Included Flags
This section contains descriptions of flags that were included implicitly
by other flags, but which do not have a permanent home at SPEC.
-
- -O2
-
Moderate level of optimization which enables most optimizations. This is the default when no "-O" option is
specified, or if no value is specified (i.e. "-O").
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
-
- -O1
-
Somewhere between -O0 and -O2.
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
-
-
- -O3
-
Like -O2, except that it enables optimizations that take longer to perform or that may generate larger code (in
an attempt to make the program run faster).
If multiple "O" options are used, with or without level numbers, the last such option is the one that is effective.
- Includes:
Using numactl to bind processes and memory to cores
For multi-copy runs or single copy runs on systems with multiple sockets, it is advantageous to bind a process to a
particular core. Otherwise, the OS may arbitrarily move your process from one core to another. This can affect
performance. To help, SPEC allows the use of a "submit" command where users can specify a utility to use to bind
processes. We have found the utility 'numactl' to be the best choice.
numactl runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a
command and inherited by all of its children. The numactl flag "--physcpubind" specifies
which core(s) to bind the process. "-l" instructs numactl to keep a process's memory on the
local node while "-m" specifies which node(s) to place a process's memory. For full details on using
numactl, please refer to your Linux documentation, 'man numactl'
Note that some older versions of numactl incorrectly interpret application arguments as its own. For
example, with the command "numactl --physcpubind=0 -l a.out -m a", numactl will interpret
a.out's "-m" option as its own "-m" option. To work around this problem, we put
the command to be run in a shell script and then run the shell script using numactl. For example:
"echo 'a.out -m a' > run.sh ; numactl --physcpubind=0 bash run.sh"
Transparent Huge Pages (THP)
THP is an abstraction layer that automates most aspects of creating, managing,
and using huge pages. It is designed to hide much of the complexity in using
huge pages from system administrators and developers. Huge pages
increase the memory page size from 4 kilobytes to 2 megabytes. This provides
significant performance advantages on systems with highly contended resources
and large memory workloads. If memory utilization is too high or memory is badly
fragmented which prevents huge pages being allocated, the kernel will assign
smaller 4k pages instead. Most recent Linux OS releases have THP enabled by default.
THP usage is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/enabled.
Possible values:
- never: entirely disable THP usage.
- madvise: enable THP usage only inside regions marked MADV_HUGEPAGE using madvise(3).
- always: enable THP usage system-wide. This is the default.
The SPEC CPU benchmark codes themselves never explicitly request huge pages, as the mechanism to do that is OS-specific
and can change over time. Libraries such as jemalloc which are used by the benchmarks may explicitly request huge pages,
and use of such libraries can make the "madvise" setting relevant and useful.
When no huge pages are immediately available and one is requested, how the system handles the request for THP creation is
controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/defrag.
Possible values:
- never: if no THP are available to satisfy a request, do not attempt to make any.
- defer: an allocation requesting THP when none are available gets normal pages while requesting THP creation in the
background.
- defer+madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3); for all
other regions it's like "defer".
- madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3). This is the
default.
- always: an allocation requesting THP when none are available will stall until some are made.
An application that "always" requests THP often can benefit from waiting for an allocation until those huge pages can be assembled.
For more information see the Linux transparent hugepage documentation.
ulimit -s <n>
Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.
ulimit -l <n>
Sets the maximum size of memory that may be locked into physical memory.
powersave -f (on SuSE)
Makes the powersave daemon set the CPUs to the highest supported frequency.
/etc/init.d/cpuspeed stop (on Red Hat)
Disables the cpu frequency scaling program in order to set the CPUs to the highest supported frequency.
LD_LIBRARY_PATH
An environment variable that indicates the location in the filesystem of bundled libraries to use when running the
benchmark binaries.
kernel/numa_balancing
This OS setting controls automatic NUMA balancing on memory mapping and process placement.
NUMA balancing incurs overhead for no benefit on workloads that are already bound to NUMA nodes.
Possible settings:
- 0: disables this feature
- 1: enables the feature (this is the default)
For more information see the numa_balancing entry in the
Linux sysctl documentation.
kernel/randomize_va_space (ASLR)
This setting can be used to select the type of process address space
randomization. Defaults differ based on whether the architecture supports
ASLR, whether the kernel was built with the CONFIG_COMPAT_BRK
option or not, or the kernel boot options used.
Possible settings:
- 0 - Turn the process address space randomization off. This is the default for architectures that do not support
this feature anyway, and kernels that are booted with the "
norandmaps" parameter.
- 1 - Randomize addresses of mmap base, stack, and VDSO pages.
This is the default if the
CONFIG_COMPAT_BRK option is enabled at kernel build time.
- 2 - Additionally enable heap randomization. This is the default if
CONFIG_COMPAT_BRK is
disabled.
Disabling ASLR can make process execution more deterministic and runtimes more consistent.
For more information see the randomize_va_space entry in the
Linux sysctl documentation.
MALLOC_CONF
The jemalloc library has tunable parameters, many of which may be changed at run-time via several mechanisms, one of which
is the MALLOC_CONF environment variable. Other methods, as well as the order in which they're referenced,
are detailed in the jemalloc documentation's TUNING section.
The options that can be tuned at run-time are everything in the jemalloc documentation's
MALLCTL NAMESPACE section that begins with
"opt.".
The options that may be encountered in SPEC CPU 2017 results are detailed here:
retain:true - Causes unused virtual memory to
be retained for later reuse rather than discarding it. This is the default for 64-bit Linux.thp:never - Attempts to never utilize huge pages
by using MADV_NOHUGEPAGE on all mappings. This option has no effect except when THP is set to
"madvise".
PGHPF_ZMEM
An environment variable used to initialize the allocated memory. Setting PGHPF_ZMEM to "Yes" has the effect of
initializing all allocated memory to zero.
GOMP_CPU_AFFINITY
This environment variable is used to set the thread affinity for threads spawned by OpenMP.
OMP_DYNAMIC
This environment variable is defined as part of the OpenMP standard.
Setting it to "false" prevents the OpenMP runtime from dynamically adjusting the number of threads to use for parallel
execution.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
OMP_SCHEDULE
This environment variable is defined as part of the OpenMP standard.
Setting it to "static" causes loop iterations to be assigned to threads in round-robin fashion in the order of the thread
number.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
OMP_STACKSIZE
This environment variable is defined as part of the OpenMP standard and controls the size of the stack for threads created
by OpenMP.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
OMP_THREAD_LIMIT
This environment variable is defined as part of the OpenMP standard and limits the maximum number of OpenMP threads that
can be created.
For more information, see chapter 4 ("Environment Variables") in the
OpenMP 4.5 Specification.
LIBOMP_NUM_HIDDEN_HELPER_THREADS
target nowait is supported via hidden helper task, which is a task not bound to any parallel region.
A hidden helper team with a number of threads is created when the first hidden helper task is encountered.
The number of threads can be configured via the environment variable LIBOMP_NUM_HIDDEN_HELPER_THREADS. The
default is 8. If LIBOMP_NUM_HIDDEN_HELPER_THREADS is 0, the hidden helper task is disabled and support
falls back to a regular OpenMP task. The hidden helper task can also be disabled by setting the environment variable
LIBOMP_USE_HIDDEN_HELPER_TASK=OFF.
- kernel.randomize_va_space (ASLR)
-
This setting can be used to select the type of process address space
randomization. Defaults differ based on whether the architecture supports
ASLR, whether the kernel was built with the CONFIG_COMPAT_BRK
option or not, or the kernel boot options used.
Possible settings:
- 0: Turn process address space randomization off.
- 1: Randomize addresses of mmap base, stack, and VDSO pages.
- 2: Additionally randomize the heap. (This is probably the default.)
Disabling ASLR can make process execution more deterministic and runtimes more consistent.
For more information see the randomize_va_space entry in the
Linux sysctl
documentation.
- Transparent Hugepages (THP)
-
THP is an abstraction layer that automates most aspects of creating, managing,
and using huge pages. It is designed to hide much of the complexity in using
huge pages from system administrators and developers. Huge pages
increase the memory page size from 4 kilobytes to 2 megabytes. This provides
significant performance advantages on systems with highly contended resources
and large memory workloads. If memory utilization is too high or memory is badly
fragmented which prevents hugepages being allocated, the kernel will assign
smaller 4k pages instead. Most recent Linux OS releases have THP enabled by default.
THP usage is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/enabled.
Possible values:
- never: entirely disable THP usage.
- madvise: enable THP usage only inside regions marked MADV_HUGEPAGE using madvise(3).
- always: enable THP usage system-wide. This is the default.
THP creation is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/defrag.
Possible values:
- never: if no THP are available to satisfy a request, do not attempt to make any.
- defer: an allocation requesting THP when none are available get normal pages while requesting THP creation in the background.
- defer+madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3); for all other regions it's like "defer".
- madvise: acts like "always", but only for allocations in regions marked MADV_HUGEPAGE using madvise(3). This is the default.
- always: an allocation requesting THP when none are available will stall until some are made.
An application that "always" requests THP often can benefit from waiting for an allocation until those huge pages can be assembled.
For more information see the Linux transparent hugepage documentation.
- Determinism Slider: (Default = Power)
-
Selects the determinism mode for the CPU:
- Power: Maximizes performance within the power limits defined by cTDP and PPT.
- Performance: Provides predictable performance across all processors of the same type.
- cTDP Control:(Default = 280)
-
Configures the maximum power that the CPU will consume, up to the
platform power limit (PPT). Valid values vary by CPU model. If value
outside the valid range is set, the CPU will automatically adjust the
value so that it does fall within the valid range. When increasing cTDP,
additional power will only be consumed up to the Package Power Limit
(PPT), which may be less than the cTDP setting.
| Model | Minimum cTDP | Maximum cTDP |
|---|
| EPYC 7773X | 225 | 280 |
| EPYC 7763 | 225 | 280 |
| EPYC 7713 | 225 | 240 |
- Package Power Limit (PPT) Control:(Default = 280)
-
Specifies the maximum power that each CPU package may consume in the system. The actual power limit is the maximum of the Package Power Limit and cTDP.
| Model | Minimum cTDP | Maximum cTDP |
|---|
| EPYC 7773X | 225 | 280 |
| EPYC 7763 | 225 | 280 |
| EPYC 7713 | 225 | 240 |
- NUMA nodes per socket:(Default = NPS4)
-
Specifies the number of desired NUMA nodes per populated socket in the system:
- NPS1: Each physical processor is a NUMA node, and memory accesses are interleaved across all memory channels directly connected to the physical processor.
- NPS2: Each physical processor is two NUMA nodes, and memory accesses are interleaved across 4 memory channels.
- NPS4: Each physical processor is four NUMA nodes, and memory accesses are interleaved across 2 memory channels.
- SMT Mode: (Default = Enabled)
-
Can be used to disable symmetric multithreading. To re-enable SMT, a POWER CYCLE is needed after selecting the 'Auto' option. WARNING - S3 is NOT SUPPORTED on systems where SMT is disabled.
- IOMMU: (Default = Enabled)
-
Enable: Enables the I/O Memory Management Unit (IOMMU), which extends the AMD64 system architecture by adding support for address translation and system memory access protection on DMA transfers from peripheral devices.
- 4-link xGMI max speed:(Default = 16Gbps)
-
xGMI (Global Memory Interface) is the Socket SP3 processor socket-to-socket interconnection topology comprised of four x16 links.
Each x16 link is comprised of 16 lanes. Each lane is comprised of two unidirectional differential signals.
Since xGMI is the interconnection between processor sockets, these xGMI settings are not applicable for 1S platforms.
NUMA-unaware workloads may need maximum xGMI bandwidth/speed while other compute efficient platforms may need to minimize xGMI power.
The xGMI speed can be lowered, lane width can be reduced from x16 to x8 (or x2), or an xGMI link can be disabled if power consumption is too high.
The default value for this option on Milan platforms is "Auto" which corresponds to "16Gbps". On platforms that support higher speeds, it can be raised to increase performance on workloads that benefit from higher cross-socket bandwidth at the cost of some additional power consumption.
- ACPI SRAT L3 Cache as NUMA Domain:
-
Enable/Disable report each L3 cache as a NUMA Domain to the OS.
Options available: Auto, Enabled, Disabled. Default setting is Auto.
- Memory Interleaving:
-
Memory interleaving is a technique that CPUs use to increase the memory bandwidth available for an application.
Without interleaving, consecutive memory blocks, often cache lines, are read from the same memory bank.
Because of this, software that reads consecutive memory must wait for a memory transfer to complete before starting the next memory access, reducing throughput and increasing latency.
By enabling memory interleaving, consecutive memory blocks are in different banks and can all contribute to the overall memory bandwidth, thus increasing throughput and lowering latency.
Values for this BIOS option can be: Auto/Disabled. Current default is Auto.(Use AGESA default value. Current is Enabled.)
- EDC:
-
Electrical Design Current. EDC is the maximum current a voltage rail can demand for a short,thermally insignificant amount of time.
VDDCR_CPU EDC limit (A)
- EDC Platform Limit:
-
EDC Platform limit (W)
For questions about the meanings of these flags, please contact the tester.
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Copyright 2017-2022 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.1.8.
Report generated on 2022-03-21 13:23:21 by SPEC CPU2017 flags formatter v5178.
![[benchmark]](https://www.spec.org/auto/cpu2017/images/benchmark.png)