CPU2017 Flag Description
ASUSTeK Computer Inc. ASUS RS520A-E11(KMPA-U16) Server System 2.20 GHz, AMD EPYC 7773X

Compilers: AMD Optimizing C/C++ Compiler Suite


Base Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Peak Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Base Portability Flags

503.bwaves_r

507.cactuBSSN_r

508.namd_r

510.parest_r

511.povray_r

519.lbm_r

521.wrf_r

526.blender_r

527.cam4_r

538.imagick_r

544.nab_r

549.fotonik3d_r

554.roms_r


Peak Portability Flags

503.bwaves_r

507.cactuBSSN_r

508.namd_r

510.parest_r

511.povray_r

519.lbm_r

521.wrf_r

526.blender_r

527.cam4_r

538.imagick_r

544.nab_r

549.fotonik3d_r

554.roms_r


Base Optimization Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Peak Optimization Flags

C benchmarks

519.lbm_r

538.imagick_r

544.nab_r

C++ benchmarks

508.namd_r

510.parest_r

Fortran benchmarks

503.bwaves_r

549.fotonik3d_r

554.roms_r

Benchmarks using both Fortran and C

521.wrf_r

527.cam4_r

Benchmarks using both C and C++

511.povray_r

526.blender_r

Benchmarks using Fortran, C, and C++

507.cactuBSSN_r


Base Other Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Peak Other Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.


Commands and Options Used to Submit Benchmark Runs

Using numactl to bind processes and memory to cores

For multi-copy runs or single copy runs on systems with multiple sockets, it is advantageous to bind a process to a particular core. Otherwise, the OS may arbitrarily move your process from one core to another. This can affect performance. To help, SPEC allows the use of a "submit" command where users can specify a utility to use to bind processes. We have found the utility 'numactl' to be the best choice.

numactl runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a command and inherited by all of its children. The numactl flag "--physcpubind" specifies which core(s) to bind the process. "-l" instructs numactl to keep a process's memory on the local node while "-m" specifies which node(s) to place a process's memory. For full details on using numactl, please refer to your Linux documentation, 'man numactl'

Note that some older versions of numactl incorrectly interpret application arguments as its own. For example, with the command "numactl --physcpubind=0 -l a.out -m a", numactl will interpret a.out's "-m" option as its own "-m" option. To work around this problem, we put the command to be run in a shell script and then run the shell script using numactl. For example: "echo 'a.out -m a' > run.sh ; numactl --physcpubind=0 bash run.sh"


Shell, Environment, and Other Software Settings

Transparent Huge Pages (THP)

THP is an abstraction layer that automates most aspects of creating, managing, and using huge pages. It is designed to hide much of the complexity in using huge pages from system administrators and developers. Huge pages increase the memory page size from 4 kilobytes to 2 megabytes. This provides significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents huge pages being allocated, the kernel will assign smaller 4k pages instead. Most recent Linux OS releases have THP enabled by default.

THP usage is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/enabled. Possible values:

The SPEC CPU benchmark codes themselves never explicitly request huge pages, as the mechanism to do that is OS-specific and can change over time. Libraries such as jemalloc which are used by the benchmarks may explicitly request huge pages, and use of such libraries can make the "madvise" setting relevant and useful.

When no huge pages are immediately available and one is requested, how the system handles the request for THP creation is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/defrag. Possible values:

An application that "always" requests THP often can benefit from waiting for an allocation until those huge pages can be assembled.
For more information see the Linux transparent hugepage documentation.

ulimit -s <n>

Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.

ulimit -l <n>

Sets the maximum size of memory that may be locked into physical memory.

powersave -f (on SuSE)

Makes the powersave daemon set the CPUs to the highest supported frequency.

/etc/init.d/cpuspeed stop (on Red Hat)

Disables the cpu frequency scaling program in order to set the CPUs to the highest supported frequency.

LD_LIBRARY_PATH

An environment variable that indicates the location in the filesystem of bundled libraries to use when running the benchmark binaries.

kernel/numa_balancing

This OS setting controls automatic NUMA balancing on memory mapping and process placement. NUMA balancing incurs overhead for no benefit on workloads that are already bound to NUMA nodes.

Possible settings:

For more information see the numa_balancing entry in the Linux sysctl documentation.

kernel/randomize_va_space (ASLR)

This setting can be used to select the type of process address space randomization. Defaults differ based on whether the architecture supports ASLR, whether the kernel was built with the CONFIG_COMPAT_BRK option or not, or the kernel boot options used.

Possible settings:

Disabling ASLR can make process execution more deterministic and runtimes more consistent. For more information see the randomize_va_space entry in the Linux sysctl documentation.

MALLOC_CONF

The jemalloc library has tunable parameters, many of which may be changed at run-time via several mechanisms, one of which is the MALLOC_CONF environment variable. Other methods, as well as the order in which they're referenced, are detailed in the jemalloc documentation's TUNING section.

The options that can be tuned at run-time are everything in the jemalloc documentation's MALLCTL NAMESPACE section that begins with "opt.".

The options that may be encountered in SPEC CPU 2017 results are detailed here:

PGHPF_ZMEM

An environment variable used to initialize the allocated memory. Setting PGHPF_ZMEM to "Yes" has the effect of initializing all allocated memory to zero.

GOMP_CPU_AFFINITY

This environment variable is used to set the thread affinity for threads spawned by OpenMP.

OMP_DYNAMIC

This environment variable is defined as part of the OpenMP standard. Setting it to "false" prevents the OpenMP runtime from dynamically adjusting the number of threads to use for parallel execution.

For more information, see chapter 4 ("Environment Variables") in the OpenMP 4.5 Specification.

OMP_SCHEDULE

This environment variable is defined as part of the OpenMP standard. Setting it to "static" causes loop iterations to be assigned to threads in round-robin fashion in the order of the thread number.

For more information, see chapter 4 ("Environment Variables") in the OpenMP 4.5 Specification.

OMP_STACKSIZE

This environment variable is defined as part of the OpenMP standard and controls the size of the stack for threads created by OpenMP.

For more information, see chapter 4 ("Environment Variables") in the OpenMP 4.5 Specification.

OMP_THREAD_LIMIT

This environment variable is defined as part of the OpenMP standard and limits the maximum number of OpenMP threads that can be created.

For more information, see chapter 4 ("Environment Variables") in the OpenMP 4.5 Specification.

LIBOMP_NUM_HIDDEN_HELPER_THREADS

target nowait is supported via hidden helper task, which is a task not bound to any parallel region. A hidden helper team with a number of threads is created when the first hidden helper task is encountered.

The number of threads can be configured via the environment variable LIBOMP_NUM_HIDDEN_HELPER_THREADS. The default is 8. If LIBOMP_NUM_HIDDEN_HELPER_THREADS is 0, the hidden helper task is disabled and support falls back to a regular OpenMP task. The hidden helper task can also be disabled by setting the environment variable LIBOMP_USE_HIDDEN_HELPER_TASK=OFF.


Operating System Tuning Parameters

cpupower:
The OS 'cpupower' utility is used to change CPU power governors settings. Available settings are:
kernel.randomize_va_space (ASLR)
This setting can be used to select the type of process address space randomization. Defaults differ based on whether the architecture supports ASLR, whether the kernel was built with the CONFIG_COMPAT_BRK option or not, or the kernel boot options used.
Possible settings: Disabling ASLR can make process execution more deterministic and runtimes more consistent. For more information see the randomize_va_space entry in the Linux sysctl documentation.
Transparent Hugepages (THP)
THP is an abstraction layer that automates most aspects of creating, managing, and using huge pages. It is designed to hide much of the complexity in using huge pages from system administrators and developers. Huge pages increase the memory page size from 4 kilobytes to 2 megabytes. This provides significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead. Most recent Linux OS releases have THP enabled by default.
THP usage is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/enabled. Possible values: THP creation is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/defrag. Possible values: An application that "always" requests THP often can benefit from waiting for an allocation until those huge pages can be assembled.
For more information see the Linux transparent hugepage documentation.

Firmware / BIOS / Microcode Settings

Determinism Slider:
This BIOS option allows for AGESA determinism to control performance.
cTDP Control:
This BIOS option is for "Configurable TDP (cTDP)", it allows user can set customized value for TDP. Available settings are:
cTDP:
TDP is an acronym for "Thermal Design Power." TDP is the recommended target for power used when designing the cooling capacity for a server. EPYC processors are able to control this target power consumption within certain limits. This capability is referred to as "configurable TDP" or "cTDP." cTDP can be used to reduce power consumption for greater efficiency, or in some cases, increase power consumption above the default value to provide additional performance. cTDP is controlled using a BIOS option.

The default EPYC cTDP value corresponds with the microprocessor's nominal TDP. The default cTDP value is set at a good balance between performance and energy efficiency. The EPYC 7763 cTDP can be reduced as low as 225W, which will minimize the power consumption for the processor under load, but at the expense of peak performance. Increasing the EPYC 7763 cTDP to 280W will maximize peak performance by allowing the CPU to maintain higher dynamic clock speeds, but will make the microprocessor less energy efficient. Note that at maximum cTDP, the CPU thermal solution must be capable of dissipating at least 280W or the EPYC 7763 processor might engage in thermal throttling under load.

The available cTDP ranges for each EPYC model are in the table below:
ModelMinimum cTDPMaximum cTDP
EPYC 7773X225280
EPYC 7573X225280
EPYC 7473X225280
EPYC 7373X225280
EPYC 7763225280
EPYC 7713225240
EPYC 7713P225240
EPYC 7663225240
EPYC 7643225240
EPYC 75F3225280
EPYC 7543225240
EPYC 7543P225240
EPYC 7513165200
EPYC 7453225240
EPYC 74F3225240
EPYC 7443165200
EPYC 7443P165200
EPYC 7413165200
EPYC 73F3225240
EPYC 7343165200
EPYC 7313155180
EPYC 7313P155180
EPYC 72F3165200
* cTDP must remain below the thermal solution design parameters or thermal throttling could be frequently encountered.
Power phase shedding:
Power phase shedding allows efficiency optimization of the voltage regulator across the variety of loads, minimizing average energy consumption by optimizing the powertrain for specific load power states. Values for this BIOS option can be: Enabled/Disabled. Current default is Enabled.
SVM Mode:
This is CPU virtualization function. With SVM enabled you'll be able to install a virtual machine on your system. Values for this BIOS option can be: Enabled/Disabled. Current default is Enabled.
SR-IOV support:
In virtualization, single root input/output virtualization or SR-IOV is a specification that allows the isolation of the PCI Express resources for manageability and performance reasons. A single physical PCI Express can be shared on a virtual environment using the SR-IOV specification. If system has SR-IOV capable PCIe Devices, this option Enables or Disables Single Root IO Virtualization Support. Values for this BIOS option can be: Enabled/Disabled. Current default is Disabled.
DRAM Scrub time:
DRAM scrubbing is a mechanism for the memory controller to periodically read all memory locations and write back corrected data. The time interval for scrubbing the entire memory can be: Disabled/1 hour/4 hours/8 hours/16 hours/24 hours/48 hours/Auto. Current default is Auto(AGESA default value).
NUMA nodes per socket:
Specifies the number of desired NUMA nodes per populated socket in the system: Current default is Auto.
APBDIS:
Application Power Management (APM) allows the processor to provide maximum performance while remaining within the specified power delivery and removal envelope. APM dynamically monitors processor activity and generates an approximation of power consumption. If power consumption exceeds a defined power limit, a P-state limit is applied by APM hardware to reduce power consumption. APM ensures that average power consumption over a thermally significant time period remains at or below the defined power limit. Set APBDIS=1 will disable Data Fabric APM and the SOC P-state will be fixed. Available settings are:
Fix SOC P-state:
To minimize variance or trade-off memory latency versus bandwidth, algorithm performance boost (APBDIS) can be set and specific hard-fused Data Fabric (SoC) P-states forced for optimized workloads sensitive to latency or throughput. Available settings are:
ACPI SRAT L3 Cache as NUMA Domain:
Each L3 Cache will be exposed as a NUMA node when enabling ACPI SRAT L3 Cache as a NUMA node. On a dual processor system, with up to 8 L3 Caches per processor, this setting will expose 16 NUMA domains. Available settings are:
Package Power Limit Control:
This BIOS option allows user can set customized value for processor package power limit(PPT). Available settings are:
DLWM Support:
Dynamic Link Width Management(DLWM) reduces xGMI lane width from x16 to x8 or x2 if xGMI links have limited traffic. DLWM feature is optimized to trade power between CPU core intensive workloads and I/O bandwidth intensiveworkloads. When link activity is above a threshold, DLWM will increase lane width from x8 to x16 at the cost of some delay, because the I/O die must disconnect the links, retrain them at the new speed and release the system back to functionality. Values for this BIOS option can be: Auto/Enabled/Disabled. Current default is Auto.(Use AGESA default value. Current is Enabled.)
Engine Boost:
ASUS individual feature with the power acceleration design to increase CPU over-all performance. Available settings are: disabled(default) and enabled. Enable it could improve performance, but comes with more power consumption.
Package Power Limit:
Set customize processor Package Power Limit (PPT) value to be used on all populated processors in the system. Current default value is 240 = Use the 240W PPT value. ***PPT will be used as the ASIC power limit***
IOMMU:
The Input-Output Memory Management Unit(IOMMU) provides several benefits and is required when using x2APIC. Enabling the IOMMU allows devices (such as the EPYC integrated SATA controller) to present separate IRQs for each attached device instead of one IRQ for the subsystem. The IOMMU also allows operating systems to provide additional protection for DMA capable I/O devices. Values for this BIOS option can be: Auto/Enabled/Disabled. Current default is Auto.(Use AGESA default value. Current is Enabled.)
Memory Interleaving:
Memory interleaving is a technique that CPUs use to increase the memory bandwidth available for an application. Without interleaving, consecutive memory blocks, often cache lines, are read from the same memory bank. Because of this, software that reads consecutive memory must wait for a memory transfer to complete before starting the next memory access, reducing throughput and increasing latency. By enabling memory interleaving, consecutive memory blocks are in different banks and can all contribute to the overall memory bandwidth, thus increasing throughput and lowering latency. Values for this BIOS option can be: Auto/Disabled. Current default is Auto.(Use AGESA default value. Current is Enabled.)

Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/ASUSTekPlatform-Settings-AMD-Milan-V1.5.html,
http://www.spec.org/cpu2017/flags/aocc320-flags-A1.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/ASUSTekPlatform-Settings-AMD-Milan-V1.5.xml,
http://www.spec.org/cpu2017/flags/aocc320-flags-A1.xml.


For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2022 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.1.8.
Report generated on 2022-03-22 10:59:45 by SPEC CPU2017 flags formatter v5178.