Intel_compiler_flags Intel Compiler, Optimization and Other flags for use by SPEChpc

Compilers: Intel Fortran/C/C++

Operating systems: Linux

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The OpenMPI Fortran driver configured for use with the Intel Fortran compiler.

]]> mpifort The OpenMPI C++ driver configured for use with the Intel C++ compiler.

]]> mpicxx The OpenMPI C driver configured for use with the Intel C compiler.

]]> mpicc The Intel MPI Fortran driver configured for use with the Intel Fortran compiler.

]]> mpiifort The Intel MPI C++ driver configured for use with the Intel C++ compiler.

]]> mpiicpc The Intel MPI C driver configured for use with the Intel C compiler.

]]> mpiicc USE std C++ libs on Linker

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]]> Disable use of reduction with variable array reduction variable (OpenMP 4.5, OpenACC 2.7) even if compiler reports support.

]]> Disable use of reduction with variable array reduction variable (OpenMP 4.5, OpenACC 2.7) even if compiler reports support.

]]> Use C99 language features.

]]> --c++14 Use C++ 17 language features.

]]> --c++17 Use C++ 14 language features.

]]> --c++14 -align array64byte specifies that analyzed arrays should be aligned to 64byte boundaries The align toggle changes how data elements are aligned. Variables and arrays are analyzed and memory layout can be altered. Specifying array64byte will look for opportunities to transform and reailgn arrays to 64byte boundaries.

]]> Determines whether the compiler uses the current Fortran Standard rules or the old Fortran 2003 rules when interpreting assignment statements. Option standard-realloc-lhs (the default), tells the compiler that when the left-hand side of an assignment is an allocatable object, it should be reallocated to the shape of the right-hand side of the assignment before the assignment occurs. This is the current Fortran Standard definition. This feature may cause extra overhead at run time. This option has the same effect as option assume realloc_lhs.

If you specify nostandard-realloc-lhs, the compiler uses the old Fortran 2003 rules when interpreting assignment statements. The left-hand side is assumed to be allocated with the correct shape to hold the right-hand side. If it is not, incorrect behavior will occur. This option has the same effect as option assume norealloc_lhs.

]]> Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.

]]> Multi-file ip optimizations that includes:
- inline function expansion
- interprocedural constant propogation
- dead code elimination
- propagation of function characteristics
- passing arguments in registers
- loop-invariant code motion

]]> (disable/enable[default] -[no-]prec-div) -prec-div improves precision of floating-point divides. It has a slight impact on speed. -no-prec-div disables this option and enables optimizations that give slightly less precise results than full IEEE division.

When you specify -no-prec-div along with some optimizations, such as -xN and -xB (Linux) or /QxN and /QxB (Windows), the compiler may change floating-point division computations into multiplication by the reciprocal of the denominator. For example, A/B is computed as A * (1/B) to improve the speed of the computation.

However, sometimes the value produced by this transformation is not as accurate as full IEEE division. When it is important to have fully precise IEEE division, do not use -no-prec-div which will enable the default -prec-div and the result is more accurate, with some loss of performance.

]]> Enable/disable(DEFAULT) use of ANSI aliasing rules in optimizations; user asserts that the program adheres to these rules. May generate Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® procesr. Optimizes for 4th, 5th and 6th generation Intel® Co processors and the Intel® Xeon® Processor E3 v3, E5 v3, E7 v3, E3 v4, E5 v4 and E7 v4 familie Available in compiler versions 13 and later.

]]> Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.

]]> Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.

]]> Enable OpenMP compilation for hpc2021.

]]> Enable OPENMP programming model for hpc2021.

]]> Chooses generally optimal flags for the target platform.

]]> -Ofast Enable the specified warning.

]]> -Wno-incompatible-function-pointer-types Puts automatic arrays and arrays created for temporary computations on the heap instead of the stack.

]]> -heap-arrays 32768