MPI2007 Flag Description
Huawei Huawei 2288H V5 (Intel Xeon Platinum 8280 CPU, 2.70 GHz)

Copyright © 2013 Intel Corporation. All Rights Reserved.

Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.

• • -GF
  • 

  • This option enables read only string-pooling optimization.

• • -Gf
  • 

  • This option enables read/write string-pooling optimization.

• • -Ob_n
  • 

  • Specifies the level of inline function expansion.

    Ob0 - Disables inlining of user-defined functions. Note that statement functions are always inlined.

    Ob1 - Enables inlining when an inline keyword or an inline attribute is specified. Also enables inlining according to the C++ language.

    Ob2 - Enables inlining of any function at the compiler's discretion.

• • -O2
  • 

  • Enables optimizations for speed. This is the generally recommended optimization level. This option also enables:
    - Inlining of intrinsics
    - Intra-file interprocedural optimizations, which include:
    - inlining
    - constant propagation
    - forward substitution
    - routine attribute propagation
    - variable address-taken analysis
    - dead static function elimination
    - removal of unreferenced variables
    - The following capabilities for performance gain:
    - constant propagation
    - copy propagation
    - dead-code elimination
    - global register allocation
    - global instruction scheduling and control speculation
    - loop unrolling
    - optimized code selection
    - partial redundancy elimination
    - strength reduction/induction variable simplification
    - variable renaming
    - exception handling optimizations
    - tail recursions
    - peephole optimizations
    - structure assignment lowering and optimizations
    - dead store elimination
    

    On IA-32 Windows platforms, -O2 sets the following:

    /Og, /Oi-, /Os, /Oy, /Ob2, /GF (/Qvc7 and above), /Gf (/Qvc6 and below), /Gs, and /Gy.

  • Includes:
    • -Oi-
    • -Gs
    • -Oy
    • -Gy
    • -Os
    • -GF
    • -Gf
    • -Ob_n
    • -Og
    • -O1
      • -unroll_n
      • -Oi-
      • -Op-
      • -Oy
      • -Gy
      • -Os
      • -GF
      • -Gf
      • -Ob_n
      • -Og
• • -Oi-
  • 

  • Disables inline expansion of all intrinsic functions.

• • -Gs
  • 

  • This option disables stack-checking for routines with 4096 bytes of local variables and compiler temporaries.

• • -Oy
  • 

  • Allows use of EBP as a general-purpose register in optimizations.

• • -Gy
  • 

  • This option tells the compiler to separate functions into COMDATs for the linker.

• • -Os
  • 

  • This option enables most speed optimizations, but disables some that increase code size for a small speed benefit.

• • -Og
  • 

  • This option enables global optimizations.

• • -O1
  • 

  • Enables optimizations for speed and disables some optimizations that
    increase code size and affect speed.
    To limit code size, this option:
    - Enables global optimization; this includes data-flow analysis, code motion, strength reduction and test replacement, split-lifetime analysis, and instruction scheduling.
    - Disables intrinsic recognition and intrinsics inlining.
    The O1 option may improve performance for applications with very large code size, many branches, and execution time not dominated by code within loops.
    On IA-32 Windows platforms, -O1 sets the following:

    /Qunroll0, /Oi-, /Op-, /Oy, /Gy, /Os, /GF (/Qvc7 and above), /Gf (/Qvc6 and below), /Ob2, and /Og

  • Includes:
    • -unroll_n
    • -Oi-
    • -Op-
    • -Oy
    • -Gy
    • -Os
    • -GF
    • -Gf
    • -Ob_n
    • -Og
• • -unroll_n
  • 

  • Tells the compiler the maximum number of times to unroll loops.

• • -Op-
  • 

  • Disables conformance to the ANSI C and IEEE 754 standards for floating-point arithmetic.

System and Other Tuning Information

This result has been formatted using multiple flags files. The "platform settings" from each of them appears next.

Platform settings from Huawei_x86_64_Intel_linux

SPEC MPI2007 Flag Description for the Intel(R) C++ Compiler for IA32 and Intel 64 applications and Intel(R) Fortran Compiler for IA32 and Intel 64 applications

Intel(R) MPI Library 4.1.1 for Linux* options and environment variables

Job startup command flags

Use this option to set the number of MPI processes to run the current arg-set.

-perhost <# of processes>

Use this option to place the indicated number of consecutive MPI processes on every host in group round robin fashion. The number of processes to start is controlled by the option -n as usual.

--parallel-startup

Use this option to allow parallel fast starting of mpd daemons under one local root. No daemon checking is performed.

-genv <ENVVAR> <value>

Use this option to set the <ENVVAR> environment variable to the specified <value> for all MPI processes.

Environment variables

I_MPI_DEVICE=<device>[:<provider>]

Select the particular network fabric to be used.

sock - Sockets

shm - Shared-memory only (no sockets)

ssm - Combined sockets + shared memory (for clusters with SMP nodes)

rdma - RDMA-capable network fabrics including InfiniBand*, Myrinet* (via DAPL*)

rdssm - Combined sockets + shared memory + DAPL* (for clusters with SMP nodes and RDMA-capable network fabrics)

I_MPI_FALLBACK_DEVICE=(enable|disable)

Set this environment variable to enable fallback to the available fabric. It is valid only for rdssm and rdma modes.

Fall back to the shared memory and/or socket fabrics if initialization of the DAPL* fabric fails. This is the default value.

Terminate the job if the fabric selected by the I_MPI_DEVICE environment variable cannot be initialized.

Platform settings from Huawei-SPECmpi2007-Platform-Settings-SKL-V1.0

SPEC MPI2007 Platform Settings for Huawei Platform system

Hardware Prefetcher:

This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Adjacent Cache Prefetch:

This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within a 128-byte sector that contains the data needed due to a cache line miss. In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Turbo Mode:

Enabling this option allows the processor cores to automatically increase its frequency and increasing performance if it is running below power, temperature.

Hyper-Threading:

Enabling this option allows to use processor resources more efficiently, enabling multiple threads to run on each core and increases processor throughput, improving overall performance on threaded software.

Power Policy(Default=Custom)

Values for this BIOS setting can be:

Efficiency: Maximize the power efficiency of the server.

Performance: Maximize the performance of the server.

Custom: Allows the user to setup all of the BIOS options according to their requirement.

Load Balance: The system's performance and consumption will be adjusted automatically according to the loading.

Cooling Configuration

The Baseboard Management Controller allows the user to adjust the fan speed manually,If the server is in a stressful environment, the CPU have high temperature, you can adjust the fan speed to 100%.

C-State

Core C3, Core C6 can be disabled for latency-sensitive applications in order to minimize latency, but disable Core C-states can also significantly limit the amount of turbo when a low number of cores are active, C3 and C6 are recommended to enable in SPEC CPU benchmark.

CPU C6 Report

Enable or disable reporting of the CPU C6 State (ACPI C3) to the OS.

Enhanced Halt State (C1E)

When set to Enabled, the processor is allowed to switch to nimimum performance and save power when idle.

Memory Patrol Scrub

This BIOS option allows the enabling/disabling of Memory Periodic Patrol Scrubber. The Memory Periodic Patrol Scrubber corrects memory soft errors so that, over the length of the system runtime, the risk of producing multi-bit and uncorrectable errors is reduced.

IMC (Integrated memory controller) Interleaving

This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs), Memory could be interleaved across sockets, memory controllers, DDR channels, Ranks. Memory is interleaved for performance and thermal distribution.

If IMC Interleaving is set to 2-way, addresses will be interleaved between the two IMCs.

If IMC Interleaving is set to 1-way, there will be no interleaving.

If IMC Interleaving is set to auto, it depends on the SNC (Sub NUMA Clustering) setting, when SNC is set to enbaled, the IMC Interleaving will be 1-way interleave, SNC is set to disabled, the IMC Interleaving will be 2-way interleave.

If SNC is disabled, IMC Interleaving should be set to 2-way. If SNC is enabled, IMC Interleaving should be set to 1-way.

Sub-NUMA Clustering（SNC）

SNC breaks up the last level cache (LLC) into disjoint clusters based on address range, with each cluster bound to a subset of the memory controllers in the system. SNC improves average latency to the LLC and memory. SNC is a replacement for the cluster on die (COD) feature found in previous processor families. For a multi-socketed system, all SNC clusters are mapped to unique NUMA (Non Uniform Memory Access) domains.

SNC AUTO supports 1-cluster or 2-clusters depending on IMC interleave. SNC and IMC interleave both AUTO will support 1-cluster 2-way IMC interleave.

SNC Enable supports Full SNC (2 clusters) and 1-way IMC interleave. Utilizes LLC capacity more efficiently and reduces latency due to core/IMC proximity. This may provide performance improvement on NUMA-aware operating systems.

SNC disable supports 1-cluster and 2-way IMC interleave, the LLC is treated as one cluster.

LLC Dead Line Allocation

In some Intel CPU caching schemes, mid-level cache (MLC) evictions are filled into the last level cache (LLC). If a line is evicted from the MLC to the LLC, the core can flag the evicted MLC lines as "dead.” This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if the option is disabled.

Values for this BIOS option can be:

Disabled: Disabling this option can save space in the LLC by never filling MLC dead lines into the LLC.

Enabled: Opportunistically fill MLC dead lines in LLC, if space is available.

Last Level Cache (LLC) Prefetch

This option configures the processor last level cache (LLC) prefetch feature as a result of the non-inclusive cache architecture. The LLC prefetcher exists on top of other prefetchers that can prefetch data into the core data cache unit (DCU) and mid-level cache (MLC). In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.

Values for this BIOS option can be:

Disabled: Disables the LLC prefetcher. The other core prefetchers are unaffected.

Enabled: Gives the core prefetcher the ability to prefetch data directly to the LLC.

Xtended Prediction Table (XPT) Prefetch

The Xtended Prediction Table (XPT) prefetcher exists on top of other prefetchers that can prefetch data into the DCU, MLC, and LLC. The XPT prefetcher will issue a speculative DRAM read request in parallel to an LLC lookup. This prefetch bypasses the LLC, saving latency. In some cases, setting this option to disabled can improve performance. Typically, setting this option to enable provides better performance.

Values for this BIOS option can be:

Enabled: Allows a read request sent to the LLC to speculatively issue a copy of the read to DRAM.

Disabled: Read requests to the LLC are not allowed to send a speculative read to DRAM.

Adaptive Double Device Data Correction (ADDDC) Sparing

Adaptive Double Device Data Correction (ADDDC), which is an enhanced feature to DDDC. This function is used to correct data errors on two memory particles, ADDDC still has single-particle multi-bit error correction capability after the first particle failure occurs and is replaced.

Values for this BIOS option can be:

Enabled: Enable the ADDDC Sparing function.

Disabled: Disable the ADDDC Sparing function.

Flag description origin markings:

	Indicates that the flag description came from the user flags file.
	Indicates that the flag description came from the suite-wide flags file.
	Indicates that the flag description came from a per-benchmark flags file.

For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2006-2010 Standard Performance Evaluation Corporation
Tested with SPEC MPI2007 v2.0.1.
Report generated on Tue Apr 2 18:30:35 2019 by SPEC MPI2007 flags formatter v1445.