SPEC Seal of Reviewal OMPM2001 Result
Copyright © 1999-2007 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer p5 575 (1900 MHz, 8 CPU)
SPECompMpeak2001 = 28035      
SPECompMbase2001 = 24805      
SPEC license # HPG0005 Tested by: IBM Test site: Austin, TX Test date: Jan-2005 Hardware Avail: Feb-2005 Software Avail: Dec-2004
Benchmark Reference
Graph Scale
310.wupwise_m 6000 176    34155       176    34155       310.wupwise_m base result bar (34155)
310.wupwise_m peak result bar (34155)
312.swim_m 6000 215    27906       179    33555       312.swim_m base result bar (27906)
312.swim_m peak result bar (33555)
314.mgrid_m 7300 505    14469       391    18650       314.mgrid_m base result bar (14469)
314.mgrid_m peak result bar (18650)
316.applu_m 4000 95.2  42016       90.6  44166       316.applu_m base result bar (42016)
316.applu_m peak result bar (44166)
318.galgel_m 5100 133    38397       110    46229       318.galgel_m base result bar (38397)
318.galgel_m peak result bar (46229)
320.equake_m 2600 215    12090       113    23097       320.equake_m base result bar (12090)
320.equake_m peak result bar (23097)
324.apsi_m 3400 144    23582       141    24151       324.apsi_m base result bar (23582)
324.apsi_m peak result bar (24151)
326.gafort_m 8700 280    31055       279    31143       326.gafort_m base result bar (31055)
326.gafort_m peak result bar (31143)
328.fma3d_m 4600 323    14224       324    14206       328.fma3d_m base result bar (14224)
328.fma3d_m peak result bar (14206)
330.art_m 6400 117    54711       117    54711       330.art_m base result bar (54711)
330.art_m peak result bar (54711)
332.ammp_m 7000 490    14272       490    14272       332.ammp_m base result bar (14272)
332.ammp_m peak result bar (14272)
SPECompMbase2001 24805        
  SPECompMpeak2001 28035        

Hardware Vendor: IBM Corporation
Model Name: IBM eServer p5 575 (1900 MHz, 8 CPU)
CPU MHz: 1900
FPU: Integrated
CPU(s) enabled: 8 cores, 8 chips, 1 core/chip (SMT on)
CPU(s) orderable: 8
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified (on chip)/chip
L3 Cache: 36MB unified (off-chip)/DCM, 8 DCM/SUT
Other Cache: None
Memory: 32 GB
Disk Subsystem: 2x36GB SCSI, 15K RPM
Other Hardware: None
OpenMP Threads: 16
Parallel: OpenMP
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 7.0 for AIX
XL Fortran Enterprise Edition V9.1 for AIX
Other Software: ESSL for AIX V4.2
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information
Tested by IBM
 Portability Flags & Environment Variables
   -qfixed used in: 310.wupwise_m, 312.swim_m, 314.mgrid_m, 316.applu_m, 324.apsi_m
   -qfixed=80 used in: 318.galgel_m
   -qsuffix=f=f90 used in: 318.galgel_m, 326.gafort_m, 328.fma3d_m
 Base Flags
   C:       -qpdf1/pdf2
            -q64 -O5 -blpdata -qalign=natural -qhot=arraypad -Q -qsmp=omp
   FORTRAN: -O5 -qhot=arraypad -qipa=noobject -qipa=partition=large -qmaxmem=-1 -qsmp=omp
 Base & Peak User Environment:
 Peak Flags:
   -qsmp=omp used in all cases
   310.wupwise_m:    basepeak=1
   312.swim_m:       -q64 -O5 -qarch=pwr3 -qtune=pwr3
   314.mgrid_m:      -O5 -q64 -qipa=partition=large
   316.applu_m:      -q64 -O4 -qhot -qmaxmem=-1
   318.galgel_m:     -q64 -O5 -qessl -lesslsmp
   320.equake_m:     -qpdf1/pdf2
                     -q64 -O5 -qessl -lesslsmp
   324.apsi_m:       -qpdf1/pdf2
                     q64 -O5 -blpdata -qalign=natural -qhot=arraypad -Q
   326.gafort_m:     -O5 -qipa=partition=large
   328.fma3d_m:      -O5 -qhot=arraypad -qipa=noobject -qipa=partition=large -qmaxmem=-1
   330.art_m:        basepeak=1
   332.ammp_m:       basepeak=1
  Alternate sources:
     Add critical region around update of linked list in parallel loop.
     Required src.alt available as ompm-purdue1-20040324.tar.gz
     Used for 330.art_m, base and peak.
  Peak sources:
     SPEC OMPL2001 source for 32bit systems modified for SPEC OMPM2001 used
     with 312.swim_m, 316.applu_m, 320.equake_m, 326.gafort_m. Available as
     ompl.32 src.alt in SPEC OMP2001 v3.0.

  APAR IY62267 was applied to AIX 5L V5.3 to achieve Mantainence Level 1.

  SMT:  Acronym for "Simultaneous Multi-Threading". A processor technology that allows
        the simultaneous execution of multiple thread contexts within a single processor
        core. (Enabled by default)
  DCM: Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
       For the 575, only one core is active per chip.
  ESSL: Engineering and Scientific Subroutine Library
  SUT: Acronym for "System Under Test"
  C:          IBM XL C for AIX invoked as xlc_r
  Fortran 90: IBM XL Fortran for AIX invoked as xlf90_r
  ulimits set to unlimited.
  Large page mode and memory affinity were set as follows:
     vmo -r -o lgpg_regions=512 -o lgpg_size=16777216 -o memory_affinity=1
     chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
     shutdown -r

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Copyright © 1999-2007 Standard Performance Evaluation Corporation

First published at SPEC.org on 03-Mar-2005

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