SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
Hewlett-Packard Company
hp AlphaServer ES45 68/1250
SPECint_rate2000 = 10.8  
SPECint_rate_base2000 = 9.80 
SPEC license # 2 Tested by: HP NH Test date: Jul-2002 Hardware Avail: Aug-2002 Software Avail: Dec-2002
Graph Scale Benchmark Base
Copies Runtime Ratio
164.gzip base result bar (6.68)
164.gzip peak result bar (6.76)
164.gzip 1 243    6.68  1 240    6.76 
175.vpr base result bar (9.97)
175.vpr peak result bar (10.2)
175.vpr 1 163    9.97  1 159    10.2  
176.gcc base result bar (10.5)
176.gcc peak result bar (11.4)
176.gcc 1 122    10.5   1 112    11.4  
181.mcf base result bar (13.0)
181.mcf peak result bar (17.0)
181.mcf 1 160    13.0   1 123    17.0  
186.crafty base result bar (11.8)
186.crafty peak result bar (11.8)
186.crafty 1 98.4  11.8   1 98.4  11.8  
197.parser base result bar (6.60)
197.parser peak result bar (8.17)
197.parser 1 316    6.60  1 256    8.17 
252.eon base result bar (11.0)
252.eon peak result bar (11.5)
252.eon 1 137    11.0   1 132    11.5  
253.perlbmk base result bar (9.16)
253.perlbmk peak result bar (10.0)
253.perlbmk 1 228    9.16  1 208    10.0  
254.gap base result bar (6.40)
254.gap peak result bar (7.78)
254.gap 1 199    6.40  1 164    7.78 
255.vortex base result bar (13.4)
255.vortex peak result bar (15.2)
255.vortex 1 164    13.4   1 145    15.2  
256.bzip2 base result bar (10.7)
256.bzip2 peak result bar (11.6)
256.bzip2 1 162    10.7   1 150    11.6  
300.twolf base result bar (11.9)
300.twolf peak result bar (11.9)
300.twolf 1 292    11.9   1 292    11.9  
  SPECint_rate_base2000 9.80   
  SPECint_rate2000 10.8  

Hardware Vendor: Hewlett-Packard Company
Model Name: hp AlphaServer ES45 68/1250
CPU: Alpha 21264C
CPU MHz: 1250
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 1 core/chip
CPU(s) orderable: 1 to 4
Parallel: No
Primary Cache: 64KB(I)+64KB(D) on chip
Secondary Cache: 16MB off chip per CPU
L3 Cache: None
Other Cache: None
Memory: 16GB
Disk Subsystem: 9 GB SCSI
Other Hardware: None
Operating System: Tru64 UNIX V5.1B
Compiler: Compaq C V6.5-011-48C5K
Spike V5.2 (506 48C5K)
Compaq C++ V6.3-010
File System: ufs
System State: Multi-user
Notes / Tuning Information
 Baseline C  : cc  -arch ev6 -fast +CFB ONESTEP 
          C++: cxx -arch ev6 -O2        ONESTEP 
   All but 252.eon: cc -g3 -arch ev6 ONESTEP
      164.gzip: -fast -O4 -non_shared +CFB 
       175.vpr: -fast -O4 -assume restricted_pointers +CFB 
       176.gcc: -fast -O4 -xtaso_short -all -ldensemalloc -none
                +CFB +IFB 
       181.mcf: -fast -xtaso_short +CFB +IFB +PFB
    186.crafty: same as base
    197.parser: -fast -O4 -xtaso_short -non_shared +CFB
       252.eon: cxx -arch ev6 -O2 -all -ldensemalloc -none 
   253.perlbmk: -fast -non_shared +CFB +IFB 
       254.gap: -fast -O4 -non_shared +CFB +IFB +PFB 
    255.vortex: -fast -non_shared +CFB +IFB
     256.bzip2: -fast -O4 -non_shared +CFB 
     300.twolf: -fast -O4 
                -ldensemalloc -non_shared +CFB +IFB

 Most benchmarks are built using one or more types of 
 profile-driven feedback.  The types used are designated
 by abbreviations in the notes:

 +CFB: Code generation is optimized by the compiler, using 
       feedback from a training run.  These commands are
       done before the first compile (in phase "fdo_pre0"):

            mkdir /tmp/pp
            rm -f /tmp/pp/${baseexe}*

       and these flags are added to the first and second compiles:

            PASS1_CFLAGS = -prof_gen_noopt -prof_dir /tmp/pp
            PASS2_CFLAGS = -prof_use       -prof_dir /tmp/pp
      (Peak builds use /tmp/pp above; base builds use /tmp/pb.)

 +IFB: Icache usage is improved by the post-link-time optimizer 
       Spike, using feedback from a training run.  These commands
       are used (in phase "fdo_postN"):  

            mv ${baseexe} oldexe
            spike oldexe -feedback oldexe -o ${baseexe}

 +PFB: Prefetches are improved by the post-link-time optimizer 
       Spike, using feedback from a training run.  These
       commands are used (in phase "fdo_post_makeN"):

            rm -f *Counts*
            mv ${baseexe} oldexe
            pixie -stats dstride oldexe 1>pixie.out 2>pixie.err
            mv oldexe.pixie ${baseexe}

       A training run is carried out (in phase "fdo_runN"), and 
       then this command (in phase "fdo_postN"):

            spike oldexe -fb oldexe -stride_prefetch -o ${baseexe}

 When Spike is used for both Icache and Prefetch improvements, 
 only one spike command is actually issued, with the Icache 
 options followed by the Prefetch options.
         vm_bigpg_enabled = 1
         vm_swap_eager = 0
         max_per_proc_address_space = 0x40000000000
         max_per_proc_data_size = 0x40000000000
         max_per_proc_stack_size = 0x40000000000
         max_proc_per_user = 2048
         max_threads_per_user = 0
         maxusers = 16384
         per_proc_address_space = 0x40000000000
         per_proc_data_size = 0x40000000000
         per_proc_stack_size = 0x40000000000
 Portability: gcc: -Dalloca=__builtin_alloca; crafty: -DALPHA
 perlbmk: -DSPEC_CPU2000_DUNIX; vortex: -DSPEC_CPU2000_LP64

For questions about this result, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 12-Nov-2002

Generated on Wed Apr 13 13:12:12 2005 by SPEC CPU2000 HTML formatter v1.01