SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer p5 595 (1900 MHz, 1 CPU)
SPECint2000 = 1452     
SPECint_base2000 = 1392     
SPEC license # 11 Tested by: IBM Test date: Jan-2005 Hardware Avail: Nov-2004 Software Avail: Dec-2004
Benchmark Reference
Runtime Ratio Graph Scale
164.gzip 1400 159    882     156    897     164.gzip base result bar (882)
164.gzip peak result bar (897)
175.vpr 1400 114    1226      114    1228      175.vpr base result bar (1226)
175.vpr peak result bar (1228)
176.gcc 1100 69.6  1581      70.6  1558      176.gcc base result bar (1581)
176.gcc peak result bar (1558)
181.mcf 1800 74.5  2417      67.6  2663      181.mcf base result bar (2417)
181.mcf peak result bar (2663)
186.crafty 1000 86.0  1163      67.6  1479      186.crafty base result bar (1163)
186.crafty peak result bar (1479)
197.parser 1800 145    1244      145    1244      197.parser base result bar (1244)
197.parser peak result bar (1244)
252.eon 1300 81.5  1594      79.1  1643      252.eon base result bar (1594)
252.eon peak result bar (1643)
253.perlbmk 1800 184    981     169    1067      253.perlbmk base result bar (981)
253.perlbmk peak result bar (1067)
254.gap 1100 86.0  1279      86.2  1276      254.gap base result bar (1279)
254.gap peak result bar (1276)
255.vortex 1900 88.4  2149      83.0  2290      255.vortex base result bar (2149)
255.vortex peak result bar (2290)
256.bzip2 1500 113    1327      118    1271      256.bzip2 base result bar (1327)
256.bzip2 peak result bar (1271)
300.twolf 3000 193    1555      187    1605      300.twolf base result bar (1555)
300.twolf peak result bar (1605)
SPECint_base2000 1392       
  SPECint2000 1452       

Hardware Vendor: IBM Corporation
Model Name: IBM eServer p5 595 (1900 MHz, 1 CPU)
CPU MHz: 1900
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 1 core/chip (SMT off)
CPU(s) orderable: 16,24,32,40,48,56,64
Parallel: No
Primary Cache: 64KBI+32KBD (on chip)
Secondary Cache: 1920KB unified (on chip)
L3 Cache: 36MB unified (off-chip)/chip, 1 chip/MCM, 8 MCM/SUT
Other Cache: None
Memory: 256 GB DDR2
Disk Subsystem: 2x36GB SCSI, 15K RPM
Other Hardware: None
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 7.0 for AIX
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information
 Portability Flags:
   176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
   186.crafty:   -DAIX
   252.eon:      srcalt=fmax_errno
   253.perlbmk:  -DSPEC_CPU2000_AIX
   300.twolf:    -DHAVE_SIGNED_CHAR

 Base Optimization Flags:
   C:    -qpdf1/pdf2
         -O5 -blpdata -D_ILS_MACROS
   C++:  -qpdf1/pdf2
         -O5 -lhmu -qalign=natural

 Peak Optimization Flags
   164.gzip:     -qpdf1/pdf2
                 fdpr -q -O3
                 -O5 -blpdata -D_ILS_MACROS -qfdpr
   175.vpr:      -qpdf1/pdf2
                 -O5 -blpdata -qalign=natural -qhot=arraypad -Q
   176.gcc:      -qpdf1/pdf2
   181.mcf:      fdpr -q -O3
                 -O5 -blpdata -qfdpr -D_ILS_MACROS
   186.crafty:   -qpdf1/pdf2
                 fdpr -q -O3
                 -O4 -q64 -qfdpr -qarch=pwr3 -qtune=pwr3 -D_ILS_MACROS
   197.parser:   basepeak=1
   252.eon:      -qpdf1/pdf2
                 -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -D_ILS_MACROS
   253.perlbmk:  -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural
   254.gap:      -qpdf1/pdf2
                  -O5 -lhmu -qalign=natural -D_ILS_MACROS -blpdata
   255.vortex:   -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural -D_ILS_MACROS -blpdata
   256.bzip2:    fdpr -q -O3
                 -O5 -blpdata -D_ILS_MACROS -qfdpr
   300.twolf:    fdpr -q -O3
                 -O5 -blpdata -qfdpr -D_ILS_MACROS

 Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
 was used with 252.eon for POSIX-compatibility.

 APAR IY62267 was applied to AIX 5L V5.3 to achieve Mantainence Level 1.

 SMT:  Acronym for "Simultaneous Multi-Threading". A processor technology that allows
       the simultaneous execution of multiple thread contexts within a single processor
       core. (Enabled by default)
 MCM:  Acronym for "Multi-Chip Module" (four dual-core processor chips + four L3-cache chips)
 SUT:  Acronym for "System Under Test"

 ulimits set to unlimited.
 Large page mode and memory affinity were set as follows:
     vmo -r -o lgpg_regions=4096 -o lgpg_size=16777216 -o memory_affinity=1
     chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
     reboot -q
 One core was deconfigured and SMT disabled at the open-firmware prompt, using the
     boot -s cpu=1 -s smt_off

For questions about this result, please contact the tester.
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Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 22-Feb-2005

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