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Copyright © 1999-2007 Standard Performance Evaluation Corporation
Hewlett-Packard Company
ProLiant BL20p G4 (1.86 GHz, Intel Xeon processor E5320)
SPECint_rate2000 = 77.9  
SPECint_rate_base2000 = 77.7  
SPEC license # 3 Tested by: Hewlett-Packard Company Test date: Feb-2007 Hardware Avail: Jan-2007 Software Avail: Nov-2006
Graph Scale Benchmark Base
Copies
Base
Runtime
Base
Ratio
Copies Runtime Ratio
164.gzip base result bar (51.9)
164.gzip peak result bar (52.0)
164.gzip 4 125    51.9   4 125    52.0  
175.vpr base result bar (56.8)
175.vpr peak result bar (57.7)
175.vpr 4 114    56.8   4 113    57.7  
176.gcc base result bar (87.2)
176.gcc peak result bar (87.2)
176.gcc 4 58.6  87.2   4 58.6  87.2  
181.mcf base result bar (66.4)
181.mcf peak result bar (67.4)
181.mcf 4 126    66.4   4 124    67.4  
186.crafty base result bar (78.7)
186.crafty peak result bar (78.6)
186.crafty 4 58.9  78.7   4 59.0  78.6  
197.parser base result bar (64.3)
197.parser peak result bar (64.7)
197.parser 4 130    64.3   4 129    64.7  
252.eon base result bar (112)
252.eon peak result bar (113)
252.eon 4 53.6  112     4 53.5  113    
253.perlbmk base result bar (101)
253.perlbmk peak result bar (101)
253.perlbmk 4 82.9  101     4 82.6  101    
254.gap base result bar (65.9)
254.gap peak result bar (65.0)
254.gap 4 77.4  65.9   4 78.6  65.0  
255.vortex base result bar (131)
255.vortex peak result bar (131)
255.vortex 4 67.4  131     4 67.4  131    
256.bzip2 base result bar (57.4)
256.bzip2 peak result bar (57.4)
256.bzip2 4 121    57.4   4 121    57.4  
300.twolf base result bar (100)
300.twolf peak result bar (100)
300.twolf 4 139    100     4 139    100    
  SPECint_rate_base2000 77.7    
  SPECint_rate2000 77.9  

Hardware
Hardware Vendor: Hewlett-Packard Company
Model Name: ProLiant BL20p G4 (1.86 GHz, Intel Xeon processor E5320)
CPU: Intel Xeon processor E5320 (1.86 GHz, 2x4 MB L2 shared, 1066 MHz bus)
CPU MHz: 1860
FPU: Integrated
CPU(s) enabled: 4 cores, 1 chip, 4 cores/chip
CPU(s) orderable: 1,2 chips
Parallel: No
Primary Cache: 32 KB I + 32 KB D on chip per core
Secondary Cache: 8 MB I+D on chip per chip (4 MB shared per 2 cores)
L3 Cache: N/A
Other Cache: N/A
Memory: 16 GB (8x2 GB PC2-5300F CL5)
Disk Subsystem: 2x72 GB 10 K SAS
Other Hardware:
Software
Operating System: Windows Server 2003 Enterprise x64 Edition, SP1
Compiler: Intel C++ Compiler for 32-bit applications,
(Version 9.1 Build 20061103Z)
Microsoft Visual Studio .NET 2003 (v7.1.3088, for libraries)
MicroQuill Smartheap Library 8.0
File System: NTFS
System State: Default
Notes / Tuning Information
 +FDO: PASS1=-Qprof_gen  PASS2=-Qprof_use

 Base tuning for C programs:   -fast         +FDO  ONESTEP=yes shlw32M.lib
 Base tuning for C++ programs: -fast -Qcxx_features +FDO  ONESTEP=yes
 Portability flags:
   176.gcc: -Dalloca=_alloca /F10000000 
   186.crafty: -DNT_i386
   253.perlbmk: -DSPEC_CPU2000_NTOS -DPERLDLL /MT
   254.gap: -DSYS_HAS_CALLOC_PROTO -DSYS_HAS_MALLOC_PROTO
 Peak tuning:
   164.gzip:     -fast               +FDO  ONESTEP=yes 
   175.vpr:      -fast               +FDO  ONESTEP=yes
   176.gcc:      basepeak=1
   181.mcf:      -fast               +FDO  
   186.crafty:   -fast -Oa           +FDO  ONESTEP=yes shlw32M.lib 
   197.parser:   -fast               +FDO  ONESTEP=yes
   252.eon:      -fast               +FDO
   253.perlbmk:  -fast -Oa           +FDO  ONESTEP=yes shlw32M.lib
   254.gap:      -fast               +FDO  ONESTEP=yes
   255.vortex:   -fast               +FDO  ONESTEP=yes shlw32M.lib
   256.bzip2:    basepeak=1
   300.twolf:    -fast               +FDO              shlw32M.lib
 BIOS Configuration Notes
   Power Regulator set to Static High
   Adjacent Sector Prefetch disabled
 Other Configuration Notes
   The start /b /wait /affinity command is used to bind CPU(s) to processes.


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Copyright © 1999-2007 Standard Performance Evaluation Corporation

First published at SPEC.org on 06-Mar-2007

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