The following are the switches/options used by SGI for the recent SPEC95
submissions:

general description:
-n32		use high performance 32bit mips-ABI
-32		use 32bit mips-ABI as defined in System V Application Binary
		 Interface, MIPS Processor Supplement 1991
-n64		use 64 bit and the calling convention defined by the new
		 mips-ABI
-LNO		option specific to the Loop Nest Optimizer
-IPA		option specific to the InterProcedural Analyzer
-TENV		option group for compilation target environment
-TARG		option group for compilation target machine
-OPT		option group which control optimization choices
-W{l,K}		option group to pass specific option to individual pass
		 directly
			l for linker
			K for KAP (-WK is equivalent to -sopt option)


specific description:

alias=typed	Apply ANSI C Standard section 6.3 to specify those
		 circumstances in which an
		object may or may not be aliased.
alias=restrict	distinct pointers are assumed to point to distinct,
		 non-overlapping objects
clone=[on/off]	clone procedures
cs2=[n]		specify size of second level cache (e.g. 4m equals 4 megabytes)
depth=[n]	inline nodes at depth <= n in the call graph.
div_split=[true/false]
		allow changing x/y into x*(recip(y))
fold_arith_limit=[n]
		Maximum # of instructions in a basic block for aggressive
		 symbolic expression simplification to be enabled
fission=[on/off]
		do loop fission
fusion=[n/on/off]
		apply loop fusion, n is aggressive level.
IEEE_arith=[n]	specify level of conformance to IEEE 754 floating pointing
		 roundoff/overflow behavior. At level 3, all mathematically
		 valid transformation is allowed.
if_conversion=[on/off]
		converts code with control flow into predicated form
inlining	do inlining (KAP)
interchange=[on/off]
		do loop interchange
ld_latency=[n]	specifies latency of loads that will miss the first level cache
min_freq=[n]	When profiling information is available, a procedure must be
		 invoked more than n/100 % of the total cycle time before it
		 will be inlined.
pf1=[on/off]	prefetch for first level cache
pf2=[on/off]	prefetch for second level cache
pr=[processor]	compile using ISA specific to the processor specified.
prefetch=0	disable generation of prefetches
prefetch_ahead=[n]
		prefetch one cache line ahead
ivpad		reorganize common block to improve cache access to members of
		 common block. This may involve adding padding between members
		 and/or breaking a common block into a collection of common
		 blocks. This is a linker flag
pad_common/
reorg_common	same effect as ivpad above, this is a compiler flag.
o=[n]		global optimize level n (KAP)
Ofast[=ipxx]	Use optimizations selected to maximize performance for the
		 given SGI target platform IPxx.  The optimizations may differ
		 for the various platforms, and will always enable the full
		 instruction set of the target platform (e.g. -mips4 for
		 an R10000).  Although the optimizations are generally safe,
		 they may affect floating point accuracy due to rearrangement
		 of computations
Olimit=[n]	disable optimization when size of program unit is > n. When n
		 is 0, program unit size is ignored and optimization process
		 will not be disabled due to compile time limit.
plimit=[n]	inline calls to a procedure until the procedure has grown to
		 size of n
r=[n]		roundoff level n (KAP)
rela_freq=[n]	When profiling information is available, for each caller/callee
		 pair, the callee is inlined only if it is invoked more than
		 n% of the time when the caller is invoked.
roundoff=[n]	Specify the level of acceptable deviation from source order
		 floating point roundoff and overflow behavior.	At level 3,
		 any mathematically valid transformation is enabled.
small_pu=[n]	procedure with size smaller than n is not subjected to the
		 plimit
so=[n] 		scalar optimize level n (KAP)
space=[n]	inline until a program expansion of n% is reached
unroll_times_max=[n]
		unroll inner loops by a maximum of n
unroll_size=[n]	sets the ceiling of maximum number of instructions for an
		 unrolled inner loop. If n = 0, the ceiling is disregarded.
unroll_analysis=[on/off]
		perform unrolling of inner loops by analysing resource and
		 processor specifics.
v6		use v6.0 version of compiler (rag).