Base Compiler Invocation
C benchmarks
-
- icc
![[user]](http://www.spec.org/auto/accel/flags/user.png)
- CC, LD
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Invoke the Intel C Compiler
Fortran benchmarks
-
- ifort
- FC, LD
-
Invoke the Intel Fortran Compiler
Compilers: Intel c/c++/fortran Compiler 16.0.0
Operating systems: Linux
Last updated: 23-Sep-2015 blw
The text for many of the descriptions below was taken from the online help for gcc.
Invoke the Intel C Compiler
Invoke the Intel Fortran Compiler
Invoke the Intel C Compiler
Invoke the Intel Fortran Compiler
![[benchmark]](http://www.spec.org/auto/accel/flags/benchmark.png)
Enable use of SIMD directive inside of loop rather than on outer loop.
Enables the use of nested SIMD statements for OpenMP.
Enables the use of nested SIMD statements for OpenMP.
Enable use of SIMD directive inside of loop rather than on outer loop.
Specify rightmost column for fixed form sources
Enable use of SIMD directive inside of loop rather than on outer loop.
Enables the use of nested SIMD statements for OpenMP.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enables the use of nested SIMD statements for OpenMP.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enable use of SIMD directive inside of loop rather than on outer loop.
No Fortran main method exists, use C equivalent instead.
Enables the use of nested SIMD statements for OpenMP.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enables the use of nested SIMD statements for OpenMP.
Enables the use of nested SIMD statements for OpenMP.
Enable use of SIMD directive inside of loop rather than on outer loop.
Specify rightmost column for fixed form sources
Enable use of SIMD directive inside of loop rather than on outer loop.
By default, 551.ppalm uses the Temperton Algorithm to compute FFTs. By defining SPEC_HOST_FFTW3, the benchmark will instead use a user suppiled FFTW3 library. The arrays passed to this library will be the host copy.
Users must specify both -DSPEC_HOST_FFTW as well as the include path to the FFTW3 interface file, fftw3.f03. They must also add the FFTW3 libary to the libraries. For example:
315.palm:
Enables the use of nested SIMD statements for OpenMP.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enables the use of nested SIMD statements for OpenMP.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enable use of SIMD directive inside of loop rather than on outer loop.
No Fortran main method exists, use C equivalent instead.
Enables the use of nested SIMD statements for OpenMP.
Enable use of SIMD directive inside of loop rather than on outer loop.
Enable use of SIMD directive inside of loop rather than on outer loop.
Specify optimization level n:
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Specify optimization level n:
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Specify optimization level n:
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) processors. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Enable levels of prefetch insertion, where 0 disables. n may be 0 through 4 inclusive. Default is 2.
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Enable levels of prefetch insertion, where 0 disables. n may be 0 through 4 inclusive. Default is 2.
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Enable levels of prefetch insertion, where 0 disables. n may be 0 through 4 inclusive. Default is 2.
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Specifies whether streaming stores are generated always - enables generation of streaming stores under the assumption that the application is memory bound auto - compiler decides when streaming stores are used (DEFAULT) never - disables generation of streaming stores
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) processors. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Enable levels of prefetch insertion, where 0 disables. n may be 0 through 4 inclusive. Default is 2.
Specifies whether streaming stores are generated always - enables generation of streaming stores under the assumption that the application is memory bound auto - compiler decides when streaming stores are used (DEFAULT) never - disables generation of streaming stores
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Enable levels of prefetch insertion, where 0 disables. n may be 0 through 4 inclusive. Default is 2.
Improve precision of FP divides (some speed impact)
Defines the accuracy (precision) for math library functions
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
This option improves precision of square root implementations. It has a slight impact on speed.
Adds the directory for include files to the search path at compile time.
Adds the library directory search path at link time
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Enable levels of prefetch insertion, where 0 disables. n may be 0 through 4 inclusive. Default is 2.
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Enable levels of prefetch insertion, where 0 disables. n may be 0 through 4 inclusive. Default is 2.
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Specifies whether streaming stores are generated always - enables generation of streaming stores under the assumption that the application is memory bound auto - compiler decides when streaming stores are used (DEFAULT) never - disables generation of streaming stores
Specify optimization level n:
May generate Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) MICs. Optimizes for a future Intel processor.
Produce symbolic debug information in object file (implies -O0 when another optimization option is not explicitly set)
Enables OpenMP support.
Enables OpenMP* offloading compilation for target pragmas. This
option only applies to Intel(R) MIC Architecture and Intel(R)
Graphics Technology. Enabled by default with -qopenmp.
Use -qno-openmp-offload to disable.
Specify kind to specify the default device for target pragmas
host - allow target code to run on host system while still doing
the outlining for offload
mic - specify Intel(R) MIC Architecture
gfx - specify Intel(R) Graphics Technology
Enable levels of prefetch insertion, where 0 disables. n may be 0 through 4 inclusive. Default is 2.
Specifies whether streaming stores are generated always - enables generation of streaming stores under the assumption that the application is memory bound auto - compiler decides when streaming stores are used (DEFAULT) never - disables generation of streaming stores
Link using FFTW 3.3.6 library for Linux. Description from FFTW:
FFTW is a C subroutine library for computing the discrete Fourier transform (DFT) in one or more dimensions, of arbitrary input size, and of both real and complex data (as well as of even/odd data, i.e. the discrete cosine/sine transforms or DCT/DST).
Platform settings
One or more of the following settings may have been applied to the testbed. If so, the "Platform Notes" section of the report will say so; and you can read below to find out more about what these settings mean.
LD_LIBRARY_PATH=<directories> (linker)
LD_LIBRARY_PATH controls the search order for both the compile-time and run-time linkers. Usually, it can be
defaulted; but testers may sometimes choose to explicitly set it (as documented in the notes in the submission), in order to
ensure that the correct versions of libraries are picked up.
STACKSIZE=<n> (Unix)
Set the size of the stack (temporary storage area) for each slave thread of a multithreaded program.
ulimit -s <n> (Unix)
Sets the stack size to n kbytes, or "unlimited" to allow the stack size to grow without limit.
Flag description origin markings:
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Indicates that the flag description came from the user flags file. |
![[suite]](http://www.spec.org/auto/accel/flags/suite.png) |
Indicates that the flag description came from the suite-wide flags file. |
|
Indicates that the flag description came from a per-benchmark flags file. |
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright 2015-2017 Standard Performance Evaluation Corporation
Tested with SPEC ACCEL v1.2.
Report generated on Wed Aug 16 15:42:42 2017 by SPEC ACCEL flags formatter v1290.