SPEC CPU2006 Flag Description for the Intel(R) C++ Compiler 9.1 for 32-bit applications and Intel(R) Fortran Compiler 9.1 for 32-bit applications

Copyright © 2006 Intel Corporation. All Rights Reserved.


Selecting one of the following will take you directly to that section:

Optimization Flags

Portability Flags

Compiler Flags

System and Other Tuning Information

Memory Array Setting: High Redundant Bit Steering (RBS)(default setting): This option enables Memory ProteXion and is the default/standard setting. Select RBS if you are not using mirroring, hot-swap, or hot-add. Redundant bit steering is the technical term for Memory ProteXion. When a single bit in a memory DIMM fails, the function known as redundant bit steering (RBS) automatically moves the affected bit to an unused bit in the memory array, removing the need to perform the ECC correction and thereby returning the memory subsystem to peak performance. The number of RBS actions that can be performed depends on the type of DIMMs installed in the server Full Array Memory Mirroring (FAMM): Select FAMM to enable memory mirroring (and to enable hot-swap). Memory mirroring reduces the amount of addressable memory by half on each chassis in the partition, but provides complete redundancy of all addressable memory. RBS is available in this mode. Hot-Add Memory (HAM): Select HAM to enable the use of the hot-add in the future. HAM provides an array layout that supports runtime hot memory add within an OS that supports that feature. This setting has lower performance and may also restrict the amount of memory that can be installed in each chassis, as addressable ranges must be reserved on each chassis for the hot add function. RBS is available in this mode. High Performance Memory Array (HPMA): HPMA optimizes the installed memory array on each chassis in the partition for maximum memory performance. Hardware correction (ECC) of a single correctable error per chip select group (CSG) is provided, but RBS is not available. Hardware Prefetch: Enables a processor mechanism that automatically fetches data and instructions into the unified second-level cache. Enabling this feature can result in higher performance on some applications and operating systems. Disabled by default.