One or more of the following settings may have been set. Please see the Notes section of the report to determine which, if any, have been modified.
KMP_AFFINITY = granularity=fine,scatter
The value for the environment variable KMP_AFFIINTY affects how the threads from an auto-parallelized program are scheduled across processors. Specifying granularity=fine selects the finest granularity level, causes each OpenMP thread to be bound to a single thread context. This ensures that there is only one thread per core on cores supporting HyperThreading Technology. Specifying scatter distributes the threads as evenly as possible across the entire system. Hence a combination of these two options will spread the threads evenly across sockets, with one thread per physical core.
OMP_NUM_THREADS
Sets the maximum number of threads to use for OpenMP* parallel regions if no other value is specified in the application. This environment variable applies to both -openmp and -parallel (Linux and Mac OS X) or /Qopenmp and /Qparallel (Windows).
Example syntax on a Windows system with 8 cores:
set OMP_NUM_THREADS=8
Adjacent Cache Line Prefetch:
This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within an 128-byte sector that contains the data needed due to a cache line miss.
In some limited cases, setting this option from the Default may improve performance. In the majority of cases, the default setting provides better performance. Users should modify this option after performing application benchmarking to verify improved performance in their environment.
Hardware Prefetch:
This BIOS option allows allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern recognition algorithm.
In some limited cases, setting this option to Disabled may improve performance. In the majority of cases, the option set to Enabled provides better performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.
Hyper-Threading Technology
This BIOS setting disables/enables Hyper-Threading (HT) Technology. HT enables the processor to allocate an additional thread to a core.
Memory Node Interleaving
This BIOS setting when set to NUMA (Non-Uniform Memory Access) configures the system memory into blocks local to each processor. A NUMA-aware operating system can use this configuration to intelligently allocate memory for optimal performance.
]]>Possible values for architecture are:
SSE Optimizes for Intel Pentium 4 processors with Streaming SIMD Extensions (SSE).
SSE2 Optimizes for Intel Pentium 4 processors with Streaming SIMD Extensions 2 (SSE2).
Default:
OFF No processor specific code is generatd by the compiler.
-O3 (maximum speed and high-level optimizations)
-Qipo (enables interprocedural optimizations across files)
-QxT (generate code specialized for Intel Pentium 4 processor and compatible Intel processors with Streaming SIMD Extensions 3)
-Qprec-div- (disable -Qprec-div) where -Qprec-div improves precision of FP divides (some speed impact)
To override one of the options set by /fast, specify that option after the -fast option on the command line. The exception is the xP or QxP option which can't be overridden. The options set by /fast may change from release to release.
]]>The O1 option may improve performance for applications with very large code size, many branches, and execution time not dominated by code within loops.
On IA-32 Windows platforms, -O1 sets the following:
/Qunroll0, /Oi-, /Op-, /Oy, /Gy, /Os, /GF (/Qvc7 and above),
/Gf (/Qvc6 and below), /Ob2, and /Og
On IA-32 Windows platforms, -O2 sets the following:
/Og, /Oi-, /Os, /Oy, /Ob2, /GF (/Qvc7 and above), /Gf (/Qvc6
and below), /Gs, and /Gy.
On Windows systems, the O3 option sets the /GF (/Qvc7 and above), /Gf (/Qvc6 and below), and /Ob2 option.
On Linux and Mac OS X systems, the O3 option sets option -fomit-frame-pointer.
On systems using IA-32 architecture or Intel64 architecture, when O3 is used with options -ax or -x (Linux) or with options /Qax or /Qx (Windows), the compiler performs more aggressive data dependency analysis than for O2, which may result in longer compilation times.
On systems using IA-64 architecture, the O3 option enables optimizations for technical computing applications (loop-intensive code): loop\ optimizations and data prefetch.
The O3 optimizations may not cause higher performance unless loop and
memory access transformations take place. The optimizations may slow
down code in some cases compared to O2 optimizations.
The O3 option is recommended for applications that have loops that heavily
use floating-point calculations and process large data sets.
If your program adheres to these rules, then this option allows the compiler to optimize more aggressively. If it doesn't adhere to these rules, then it can cause the compiler to generate incorrect code.
]]>This option requires that the size of the program executable never exceeds 2**32 bytes and all data values can be represented within 32 bits. If the program can run correctly in a 32-bit system, these requirements are implicitly satisfied. If the program violates these size restrictions, unpredictable behavior might occur.
]]>It does not affect variables that have the SAVE attribute or ALLOCATABLE attribute, or variables that appear in an EQUIVALENCE statement or in a common block.
This option may provide a performance gain for your program, but if your program depends
on variables having the same value as the last time the routine was invoked, your program
may not function properly.
If you want to cause variables to be placed in static memory, specify /Qsave (Windows).
This option selects the method that the register allocator uses to partition each routine into regions.
When setting default is in effect, the compiler attempts to optimize the tradeoff between compile-time
performance and generated code performance.
This option is only relevant when optimizations are enabled (O1 or higher).
Possible values are:
always: Enables generation of streaming stores for optimization. The compiler optimizes under the assumption that the application is memory bound.
never : Disables generation of streaming stores for optimization. Normal stores are performed.
auto : Lets the compiler decide which instructions to use.
On IA-32 architecture and Intel 64 architecture, this option enables prefetching when higher optimization levels are specified.
]]>With some optimizations, such as -xSSE2 (Linux) or /QxSSE2 (Windows), the compiler may change floating-point division computations into multiplication by the reciprocal of the denominator. For example, A/B is computed as A * (1/B) to improve the speed of the computation.
However, sometimes the value produced by this transformation is not as accurate as full IEEE division. When it is important to have fully precise IEEE division, use this option to disable the floating-point division-to-multiplication optimization. The result is more accurate, with some loss of performance.
If you specify -no-prec-div (Linux and Mac OS X) or /Qprec-div- (Windows), it enables optimizations that give slightly less precise results than full IEEE division.
Default: -prec-div or/Qprec-div
]]>-Qscalar-rep- disables this feature. (default)
]]>-Qvec-guard-write- disables this feature. (default)
]]>By default, this feature is OFF.
]]>(processor)indicates the processor for which code is generated. Many of the following descriptions refer to Intel® Streaming SIMD Extensions
Host
Can generate instructions for the highest instruction set available on the compilation
host processor.
On Intel processors, this may correspond to the most suitable –x (Linux* and Mac OS* X)
or /Qx (Windows*) option. On non-Intel processors, this may correspond to the most suitable
–m (Linux and Mac OS X) or /arch (Windows) option. The resulting executable may not run on
a processor different from the host in the following cases:
If the processor does not support all of the instructions supported by the host processor.
If the host is an Intel processor and the other processor is a non-Intel processor.
AVX
Optimizes for Intel processors that support Intel® Advanced Vector Extensions (Intel® AVX).
SSE4.2
Can generate Intel® SSE4 Efficient Accelerated String and Text Processing instructions
supported by Intel® Core™ i7 processors. Can generate Intel® SSE4 Vectorizing Compiler
and Media Accelerator, Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize
for the Intel® Core™ processor family.
SSE4.1
Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator instructions for
Intel processors. Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions and it
can optimize for Intel® 45nm Hi-k next generation Intel® Core™ microarchitecture.
This replaces value S, which is deprecated.
SSE3_ATOM
Optimizes for the Intel® Atom™ processor and Intel® Centrino® Atom™ Processor Technology.
Can generate MOVBE instructions, depending on the setting of option -minstruction
(Linux and Mac OS) or /Qinstruction (Windows).
SSSE3
Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions for Intel processors and it
can optimize for the Intel® Core™2 Duo processor family. For Mac OS* X systems, this
value is only supported on Intel® 64 architecture. This replaces value T, which is
deprecated.
SSE3
Can generate Intel® SSE3, SSE2, and SSE instructions for Intel processors and it can
optimize for processors based on Intel® Core™ microarchitecture and Intel
NetBurst® microarchitecture. For Mac OS* X systems, this value is only supported on
IA-32 architecture.This replaces value P, which is deprecated.
SSE2
Can generate Intel® SSE2 and SSE instructions for Intel processors, and it can
optimize for Intel® Pentium® 4 processors, Intel® Pentium® M processors, and
Intel® Xeon® processors with Intel® SSE2. This value is not available on Mac OS* X
systems. This replaces value N, which is deprecated.
Default
Windows systems: None
Linux systems: None
Mac OS X systems using IA-32 architecture: SSE3
Mac OS X systems using Intel® 64 architecture: SSSE3
On Windows systems, if neither /Qx nor /arch is specified, the default is /arch:SSE2.
On Linux systems, if neither -x nor -m is specified, the default is -msse2.
Description
This option tells the compiler to generate optimized code specialized for the Intel
processor that executes your program. It also enables optimizations in addition to
Intel processor-specific optimizations. The specialized code generated by this
option may run only on a subset of Intel processors.
This option can enable optimizations depending on the argument specified. For example, it may enable Intel® Streaming SIMD Extensions 4 (Intel® SSE4), Intel® Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3), Intel® Streaming SIMD Extensions 3 (Intel® SSE3), Intel® Streaming SIMD Extensions 2 (Intel® SSE2), or Intel® Streaming SIMD Extensions (Intel® SSE) instructions.
The binaries produced by these values will run on Intel processors that support all of the features for the targeted processor. For example, binaries produced with SSE3 will run on an Intel® Core™ 2 Duo processor, because that processor completely supports all of the capabilities of the Intel® Pentium® 4 processor, which the SSE3 value targets. Specifying the SSSE3 value has the potential of using more features and optimizations available to the Intel® Core™ 2 Duo processor.
Do not use processor values to create binaries that will execute on a processor that is not compatible with the targeted processor. The resulting program may fail with an illegal instruction exception or display other unexpected behavior. For example, binaries produced with SSE3 may produce code that will not run on Intel® Pentium® III processors or earlier processors that do not support SSE3 instructions.
Compiling the function main() with any of the processor values produces binaries that display a fatal run-time error if they are executed on unsupported processors. For more information, see Optimizing Applications.
If you specify more than one processor value, code is generated for only the highest-performing processor specified. The highest-performing to lowest-performing processor values are: SSE4.2, SSE4.1, SSSE3, SSE3, SSE2.Note that processor values AVX and SSE3_ATOM do not fit within this group.
Compiler options m and arch produce binaries that should run on processors not made by Intel that implement the same capabilities as the corresponding Intel processors.
Previous value O is deprecated and has been replaced by option -msse3 (Linux and Mac OS X) and option /arch:SSE3 (Windows).
Previous values W and K are deprecated. The details on replacements are as follows:
There is no exact replacement for K. However, on Windows systems, /QxK is interpreted as /arch:IA32; on Linux systems, -xK is interpreted as -mia32. You can also do one of the following:
The -x and /Qx options enable additional optimizations not enabled with option -m or option /arch.
On Windows* systems, options /Qx and /arch are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning. Similarly, on Linux* and Mac OS* X systems, options -x and -m are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning.
]]>Ob0 - Disables inlining of user-defined functions. Note that statement functions are always inlined.
Ob1 - Enables inlining when an inline keyword or an inline attribute is specified. Also enables inlining according to the C++ language.
Ob2 - Enables inlining of any function at the compiler's discretion.
]]>