SPEC CPU2006 Flag Description for the Intel(R) Compiler 11.0 on Windows for IA32 and Intel 64 Applications

Sections

Selecting one of the following will take you directly to that section:


Optimization Flags


Portability Flags


Compiler Flags


System and Other Tuning Information

Platform settings

One or more of the following settings may have been set. Please see the Notes section of the report to determine which, if any, have been modified.

Adjacent Cache Line Prefetch:

This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within an 128-byte sector that contains the data needed due to a cache line miss.

In some limited cases, setting this option from the Default may improve performance. In the majority of cases, the default setting provides better performance. Users should modify this option after performing application benchmarking to verify improved performance in their environment.

Hardware Prefetch:

This BIOS option allows allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern recognition algorithm.

In some limited cases, setting this option to Disabled may improve performance. In the majority of cases, the option set to Enabled provides better performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.

Hyper-Threading Technology

This BIOS setting disables/enables Hyper-Threading (HT) Technology. HT enables the processor to allocate an additional thread to a core.

Memory Node Interleaving

This BIOS setting when set to NUMA (Non-Uniform Memory Access) configures the system memory into blocks local to each processor. A NUMA-aware operating system can use this configuration to intelligently allocate memory for optimal performance.