SPEC(R) CINT2006 Summary IBM Corporation IBM BladeCenter HS21 (Intel Xeon X5355) Thu Apr 12 02:49:11 2007 CPU2006 License: 11 Test date: Apr-2007 Test sponsor: IBM Corporation Hardware availability: Apr-2007 Tested by: IBM Corporation Software availability: Aug-2006 Base Base Base Peak Peak Peak Benchmarks Ref. Run Time Ratio Ref. Run Time Ratio -------------- ------ --------- --------- ------ --------- --------- 400.perlbench 9770 505 19.4 * 400.perlbench 9770 505 19.4 S 400.perlbench 9770 505 19.4 S 401.bzip2 9650 699 13.8 S 401.bzip2 9650 698 13.8 S 401.bzip2 9650 698 13.8 * 403.gcc 8050 734 11.0 S 403.gcc 8050 732 11.0 S 403.gcc 8050 733 11.0 * 429.mcf 9120 512 17.8 S 429.mcf 9120 512 17.8 * 429.mcf 9120 512 17.8 S 445.gobmk 10490 604 17.4 S 445.gobmk 10490 604 17.4 S 445.gobmk 10490 604 17.4 * 456.hmmer 9330 827 11.3 * 456.hmmer 9330 827 11.3 S 456.hmmer 9330 827 11.3 S 458.sjeng 12100 746 16.2 * 458.sjeng 12100 746 16.2 S 458.sjeng 12100 746 16.2 S 462.libquantum 20720 1380 15.0 * 462.libquantum 20720 1380 15.0 S 462.libquantum 20720 1380 15.0 S 464.h264ref 22130 791 28.0 * 464.h264ref 22130 791 28.0 S 464.h264ref 22130 791 28.0 S 471.omnetpp 6250 535 11.7 S 471.omnetpp 6250 535 11.7 * 471.omnetpp 6250 535 11.7 S 473.astar 7020 562 12.5 S 473.astar 7020 562 12.5 S 473.astar 7020 562 12.5 * 483.xalancbmk 6900 351 19.7 * 483.xalancbmk 6900 351 19.7 S 483.xalancbmk 6900 351 19.7 S ============================================================================== 400.perlbench 9770 505 19.4 * 401.bzip2 9650 698 13.8 * 403.gcc 8050 733 11.0 * 429.mcf 9120 512 17.8 * 445.gobmk 10490 604 17.4 * 456.hmmer 9330 827 11.3 * 458.sjeng 12100 746 16.2 * 462.libquantum 20720 1380 15.0 * 464.h264ref 22130 791 28.0 * 471.omnetpp 6250 535 11.7 * 473.astar 7020 562 12.5 * 483.xalancbmk 6900 351 19.7 * SPECint(R)_base2006 15.6 SPECint2006 Not Run HARDWARE -------- CPU Name: Intel Xeon X5355 CPU Characteristics: 1333MHz system bus CPU MHz: 2667 FPU: Integrated CPU(s) enabled: 8 cores, 2 chips, 4 cores/chip CPU(s) orderable: 1,2 chips Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 8 MB I+D on chip per chip, 4 MB shared / 2 cores L3 Cache: None Other Cache: None Memory: 8 GB (8 x 1GB DDR2-5300F ECC) Disk Subsystem: 1 x 74 GB SAS, 10000 RPM Other Hardware: Memory and I/O Expansion Unit (P/N 42C1600) SOFTWARE -------- Operating System: Microsoft Windows Server 2003 Enterprise x64 Edition + SP1 (64-bit) Compiler: Intel C++ Compiler for IA32 version 9.1 Build no 20060816 Microsoft Visual Studio .Net 2003 (for libraries) Auto Parallel: No File System: NTFS System State: Default Base Pointers: 32-bit Peak Pointers: Not Applicable Other Software: Smart Heap Library, Version 8 Base Compiler Invocation ------------------------ C benchmarks: icl -Qvc7.1 -Qc99 C++ benchmarks: icl -Qvc7.1 Base Portability Flags ---------------------- 403.gcc: -DSPEC_CPU_WIN32 464.h264ref: -DSPEC_CPU_NO_INTTYPES -DWIN32 Base Optimization Flags ----------------------- C benchmarks: -fast /F512000000 shlw32m.lib -link /FORCE:MULTIPLE C++ benchmarks: -fast -Qcxx_features /F512000000 shlw32m.lib -link /FORCE:MULTIPLE Base Other Flags ---------------- C benchmarks: 403.gcc: -Dalloca=_alloca The flags file that was used to format this result can be browsed at http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090714.html You can also download the XML flags source by saving the following link: http://www.spec.org/cpu2006/flags/Intel-ic91-flags.20090714.xml SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2014 Standard Performance Evaluation Corporation Tested with SPEC CPU2006 v1.0. Report generated on Tue Jul 22 12:06:29 2014 by CPU2006 ASCII formatter v6932. Originally published on 15 May 2007.