SPEC CPU20017 Platform Settings for Epsylon systems based on AMD Solutions

Operating System Tuning Parameters

sysctl -w vm.drop_caches=3 - is used to clear filesystem caches at run-time.

Firmware / BIOS / Microcode Settings

Determinism Control:
This option allows user can set customized determinism slider mode to control performance.
Available settings are: [Auto] and [Manual]
Determinism Enable:
This option allows for AGESA determinism to control performance.
Available settings are: [Performane], [Power] and [Auto]
TDP Control:
This option is for "Configurable TDP (cTDP)", it allows user set customized value for TDP.
Available settings are: [Auto] and [Manual]
TDP is the recommended target for power used when designing the cooling capacity for a server. EPYC processors are able to control this target power consumption within certain limits. This capability is referred to as "configurable TDP" or "cTDP." TDP can be used to reduce power consumption for greater efficiency, or in some cases, increase power consumption above the default value to provide additional performance.
TDP is controlled using a BIOS option.

The default EPYC TDP value corresponds with the microprocessor's nominal TDP. The default TDP value is set at a good balance between performance and energy efficiency. Decrese the EPYC CPU TDP, which will minimize the power consumption for the processor under load, but at the expense of peak performance. Increasing the EPYC CPU TDP will maximize peak performance by allowing the CPU to maintain higher dynamic clock speeds, but will make the microprocessor less energy efficient. Note that at maximum TDP, the CPU thermal solution must be capable of dissipating at least highest energy peak or the EPYC processor might engage in thermal throttling under load.

The available TDP ranges for each EPYC model are in the table below:
ModelMinimum TDPMaximum TDP
EPYC 7763225280
EPYC 7713225240
EPYC 7713P225240
EPYC 7663225240
EPYC 7643225240
EPYC 75F3225280
EPYC 7543225240
EPYC 7543P225240
EPYC 7513165200
EPYC 7453225240
EPYC 74F3225240
EPYC 7443165200
EPYC 7443P165200
EPYC 7413165200
EPYC 73F3225240
EPYC 7343165200
EPYC 7313155180
EPYC 7313P155180
EPYC 72F3165200
* TDP must remain below the thermal solution design parameters or thermal throttling could be frequently encountered.
Power phase shedding:
Power phase shedding allows efficiency optimization of the voltage regulator across the variety of loads, minimizing average energy consumption by optimizing the powertrain for specific load power states.
Available options are: [Enabled] and [Disabled].
SVM Mode:
This option stand for CPU virtualization function. What it allow user to install the virtual machnine.
Available settings are: [Enable] and [Disable]
SR-IOV Support:
This option stand for sharing the PCIe. Single Root Input/Output Virtualization (SR-IOV) this option allows isolate the PCI Express resources for manageability and performance reasons for Virtualization. A single physical PCI Express can be shared on a virtual environment using the SR-IOV specification. If system has SR-IOV capable PCIe Devices, this option Enables or Disables Single Root IO Virtualization Support.
Available settings are: [Enable] and [Disable]
DRAM Scrub time:
This option is a mechanism for the memory controller to periodically read all memory locations and write back corrected data.
Available settings are:[Disable], [1 hour], [4 hours], [8 hours], [16 hours], [24 hours], [48 hours] and [Auto]
NUMA nodes per socket:
Specifies the number of desired NUMA nodes per populated socket in the system:
Avalible settins are: [NPS1], [NPS2], [NPS4], [Auto]
Application Power Management (APM) allows the processor to provide maximum performance while remaining within the specified power delivery and removal envelope. APM dynamically monitors processor activity and generates an approximation of power consumption. If power consumption exceeds a defined power limit, a P-state limit is applied by APM hardware to reduce power consumption. APM ensures that average power consumption over a thermally significant time period remains at or below the defined power limit. Set APBDIS=1 will disable Data Fabric APM and the SOC P-state will be fixed.
Available settings are: [0], [1], [Auto]
Fix SOC P-state:
To minimize variance or trade-off memory latency versus bandwidth, algorithm performance boost (APBDIS) can be set and specific hard-fused Data Fabric (SoC) P-states forced for optimized workloads sensitive to latency or throughput.
Available settings are: [P0], [P1], [P2], [P3] and [Auto]
ACPI SRAT L3 Cache as NUMA Domain:
Each L3 Cache will be exposed as a NUMA node when enabling ACPI SRAT L3 Cache as a NUMA node. On a dual processor system, with up to 8 L3 Caches per processor, this setting will expose 16 NUMA domains.
Available settings are: [Auto] and [Enable]
Package Power Limit Control:
This option allows user can set customized value for processor package power limit (PPT).
Available settings are: [Auto] and [Manual]
DLWM Support:
Dynamic Link Width Management(DLWM) reduces xGMI lane width from x16 to x8 or x2 if xGMI links have limited traffic. DLWM feature is optimized to trade power between CPU core intensive workloads and I/O bandwidth intensive workloads. When link activity is above a threshold, DLWM will increase lane width from x8 to x16 at the cost of some delay, because the I/O die must disconnect the links, retrain them at the new speed and release the system back to functionality.
Avalible settings are: [Enable], [Disable] and [Auto]
Engine Boost:
ASUS individual feature with the power acceleration design to increase CPU over-all performance.
Available settings are: [Disabled], [Normal], and [Aggressive]
Package Power Limit (PPT):
Set customize processor Package Power Limit (PPT) value to be used on all populated processors in the system.
***PPT will be used as the ASIC power limit***
The Input-Output Memory Management Unit(IOMMU) provides several benefits and is required when using x2APIC. IOMMU allows devices (such as the EPYC integrated SATA controller) to present separate IRQs for each attached device instead of one IRQ for the subsystem. The IOMMU also allows operating systems to provide additional protection for DMA capable I/O devices.
Avalibe settings are: [Enable], [Disable] and [Auto]
Memory Interleaving:
Memory interleaving is a technique that CPUs use to increase the memory bandwidth available for an application. Without interleaving, consecutive memory blocks, often cache lines, are read from the same memory bank. Because of this, software that reads consecutive memory must wait for a memory transfer to complete before starting the next memory access, reducing throughput and increasing latency.
By enabling memory interleaving, consecutive memory blocks are in different banks and can all contribute to the overall memory bandwidth, thus increasing throughput and lowering latency. Avalibe settings are: [Auto] and [Disabled]