Hardware Prefetcher:
This BIOS option allows the enabling/disabling of a processor mechanism to prefetch data into the cache according to a pattern-recognition algorithm. This default setting is "Enable".
In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.
Adjacent Cache Prefetch:
This BIOS option allows the enabling/disabling of a processor mechanism to fetch the adjacent cache line within a 128-byte sector that contains the data needed due to a cache line miss. This default setting is "Enable".
In some cases, setting this option to Disabled may improve performance. Users should only disable this option after performing application benchmarking to verify improved performance in their environment.
DCU Streamer Prefetcher:
This BIOS option allows enabling/disabling the function of Data Cache Unit (DCU) Streamer prefetcher. This default setting is "Enable".
If this option sets to "Enable", when the DCU Streamer prefetcher detects multiple loads from the same line done within a time limit, it prefetches the next line into the L1 data cache.
Hyper-Threading [ALL]:
Disabling Intel's Hyper-Threading Technology reduces the number of threads per core to 1. The default is "Enable"; in this case each core provides additional resources for executing up to 2 threads in parallel.
SNC:
Sub NUMA Cluster (SNC) breaks up the last-level cache (LLC) into two disjoint clusters based on address range, with each cluster bound to one memory controllers in the system. SNC improves average latency to the LLC and memory. SNC is a replacement for the cluster on die (COD) feature found in previous processor families. For a multi-socketed system, all SNC clusters are mapped to unique NUMA (Non Uniform Memory Access) domains. If this option is disabled, the LLC is treated as one cluster. If this option is enabled and IMC Interleaving is 1-way Interleave, utilizes LLC capacity more efficiently and reduces latency due to core/IMC proximity. This may provide performance improvement on NUMA-aware operating systems. This default setting is "Enable".
IMC Interleaving:
This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs). There are two IMCs per socket in Skylake. If IMC Interleaving is set to 2-way Interleave, addresses will be interleaved between the two IMCs. If IMC Interleaving is set to 1-way Interleave, there will be no interleaving. If SNC is enabled, IMC Interleaving should be set to 1-way Interleave. This default setting is "Auto".
Stale AtoS:
The in-memory directory has three states: invalid (I), snoopAll (A), and shared (S). Invalid (I) state means the data is clean and does not exist in any other socket`s cache. The snoopAll (A) state means the data may exist in another socket in exclusive or modified state. Shared (S) state means the data is clean and may be shared across one or more socket`s caches. When doing a read to memory, if the directory line is in the A state we must snoop all the other sockets because another socket may have the line in modified state. If this is the case, the snoop will return the modified data. However, it may be the case that a line is read in A state and all the snoops come back a miss. This can happen if another socket read the line earlier and then silently dropped it from its cache without modifying it. If this option is enabled, in the situation where a line in A state returns only snoop misses, the line will transition to S state. That way, subsequent reads to the line will encounter it in S state and not have to snoop, saving latency and snoop bandwidth. This default setting is "Disable".
LLC dead Line Alloc:
In the Skylake non-inclusive cache scheme, mid-level cache (MLC) evictions are filled into the last-level cache (LLC). If a line is evicted from the MLC to the LLC, the core can flag the evicted MLC lines as "dead." This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if this option is disabled. However, if this option is enabled, the LLC can opportunistically fill dead lines into the LLC if there is free space available. This default setting is "Enable".
ENERGY_PERF_BIAS_CFG mode:
This item decides the energy efficiency policy which is the energy per performance rate. If the highest performance is preferred, this option should be set to "Performance". This default setting is "Balanced Performance".
Patrol Scrub:
Patrol Scrub is a mechanism for memory controller to periodically read all memory. Corrected read data is written back to memory when a correctable error is detected. This default setting is "Enable".
Demand Scrub:
Demand Scrub is a mechanism for memory controller to correct a correctable error in memory. Corrected read data is sent to the requestor and written back to memory. This default setting is "Enable".
Link Frequency Select:
This option selects the upper limit of the UPI link speed. This default setting is "Auto", which configures the highest supported UPI link speed automatically.