SPEC CPU2017 Flag Description for Quanta Computer Inc.

Operating System Tuning Parameters

OS Tuning


Used to set user limits of system-wide resources. Provides control over resources available to the shell and processes started by it. Some common ulimit commands may include:

Performance Governors (Linux):

In-kernel CPU frequency governors are pre-configured power schemes for the CPU. The CPUfreq governors use P-states to change frequencies and lower power consumption. The dynamic governors can switch between CPU frequencies, based on CPU utilization to allow for power savings while not sacrificing performance.

Other options beside a generic performance governor can be set, such as the Performance governor and Powersave governor:

--governor , -g

The governor defines the power characteristics of the system CPU, which in turn affects CPU performance. Each governor has its own unique behavior, purpose, and suitability in terms of workload.

On many Linux systems one can set the governor for all CPUs through the cpupower utility with following commands:

Tuning Kernel parameters:

The following Linux Kernel parameters were tuned to better optimize performance of some areas of the system:

kernel.randomize_va_space (ASLR)

This setting can be used to select the type of process address space randomization. Defaults differ based on whether the architecture supports ASLR, whether the kernel was built with the CONFIG_COMPAT_BRK option or not, or the kernel boot options used.

Possible settings:

Disabling ASLR can make process execution more deterministic and runtimes more consistent.

For more information see the randomize_va_space entry in the "https://www.kernel.org/doc/Documentation/sysctl/kernel.txt" Linux sysctl documentation

Transparent Hugepages (THP)

THP is an abstraction layer that automates most aspects of creating, managing, and using huge pages. It is designed to hide much of the complexity in using huge pages from system administrators and developers. Huge pages increase the memory page size from 4 kilobytes to 2 megabytes. This provides significant performance advantages on systems with highly contended resources and large memory workloads. If memory utilization is too high or memory is badly fragmented which prevents hugepages being allocated, the kernel will assign smaller 4k pages instead. Most recent Linux OS releases have THP enabled by default.

THP usage is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/enabled .

Possible values:

THP creation is controlled by the sysfs setting /sys/kernel/mm/transparent_hugepage/defrag.

Possible values:

An application that "always" requests THP often can benefit from waiting for an allocation until those huge pages can be assembled.

For more information see the "https://www.kernel.org/doc/Documentation/vm/transhuge.txt" Linux transparent hugepage documentation.

Firmware / BIOS / Microcode Settings

Determinism Control:
This BIOS option allows user to choose AGESA determinism control. Available settings are:
Determinism Slider:
Selects the determinism mode for the CPU:
cTDP Control(Configurable TDP):
TDP is an acronym for “Thermal Design Power.” TDP is the recommended target for power used when designing the cooling capacity for a server. EPYC processors are able to control this target power consumption within certain limits. This capability is referred to as “configurable TDP” or "cTDP." cTDP can be used to reduce power consumption for greater efficiency, or in some cases, increase power consumption above the default value to provide additional performance. cTDP is controlled using a BIOS option.
The default EPYC cTDP value corresponds with the microprocessor’s nominal TDP. For the EPYC 7601, the default value is 180W. The default cTDP value is set at a good balance between performance and energy efficiency. The EPYC 7601 cTDP can be reduced as low as 165W, which will minimize the power consumption for the processor under load, but at the expense of peak performance. Increasing the EPYC 7601 cTDP to 200W will maximize peak performance by allowing the CPU to maintain higher dynamic clock speeds, but will make the microprocessor less energy efficient. Note that at maximum cTDP, the CPU thermal solution must be capable of dissipating at least 200W or the EPYC 7601 processor might engage in thermal throttling under load.
The available cTDP ranges for each EPYC model are in the table below:
Model Nominal TDP Minimum cTDP Maximum cTDP**
EPYC 9654 360 320 400
EPYC 9654P 360 320 400
EPYC 9754 360 320 400
Package Power Limit (PPT) Control:
Specifies the maximum power that each CPU package may consume in the system. The actual power limit is the maximum of the Package Power Limit and cTDP. Available settings are:
NUMA nodes per socket (NPS):
Non-Uniform Memory Architecture (NUMA) enables the CPU cores to access memory via NUMA domains / nodes. Users can specify the number of desired NUMA nodes per populated socket in the system:
ACPI SRAT L3 Cache as NUMA Domain:
Enable the option to report each L3 cache as a NUMA domain to BIOS ACPI System Resource Affinity Table (SRAT):
SMT Control:
Can be used to disable symmetric multithreading. To re-enable SMT, a POWER CYCLE is needed after selecting the 'Auto' option. WARNING - S3 is NOT SUPPORTED on systems where SMT is disabled.
L1 Stream HW Prefetcher:
uses the history of L1 cache memory access patterns to fetch additional sequential lines in ascending or descending order.:
L2 Stream HW Prefetcher:
uses the history of L2 cache memory access patterns to fetch additional sequential lines in ascending or descending order.
Memory interleaving:
This setting allows interleaved memory accesses across multiple memory channels in each socket, providing higher memory bandwidth.
Enable: Enables the I/O Memory Management Unit (IOMMU), which extends the AMD64 system architecture by adding support for address translation and system memory access protection on DMA transfers from peripheral devices.
APBDIS is an IO Boost disable on uncore. For any system user that needs to block these uncore optimizations that are impacting base core clock speed, we are exposing a method to disable this behavior called APBDis. This locks the fabric clock to the non-boosted speeds. Available settings are:
Fixed SOC Pstate:
Specifying a fixed SOC P-state. this option is available if APBDIS is enabled. Available settings are:
ACPI CST C2 Latency:
Enter in microseconds (decimal value).Larger C2 latency values will reduce the number of C2 transitions and reduce C2 residency. Fewer transitions can help when performance is sensitive to the latency of C2 entry and exit. Higher residency can improve performance by allowing higher frequency boost and reduce idle core power.

Last updated Aug. 15, 2023.