SPEC CPU2017 Platform Settings for Tyrone Systems

Firmware / BIOS / Microcode Settings

Hyper-Threading (ALL): (Default="Enable")

Enabled Hyper Threading (Software Methos to Enable/Disable logical Processor.

Monitor/MWait: (Default = "Auto")

Sets up an address range used to monitor write-back stores. Enables a logical processor to enter into an optimized state while waiting for a write-back store to the address range set up by the MONITOR instruction.

Intel Virtualization Technology: (Default = "Disabled")

When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology

Power Technology: (Default = "Max Performance")
CPU C6 Report: (Default = "Auto")

Allows the BIOS to report the CPU C6 State (ACPI C3) to the operating system. During the CPU C6 State, the power to all cache is turned off.

Enhanced Halt State (C1E): (Default = "Enable")

Power saving feature where, when enabled, idle processor cores will halt.

Hardware P-states: (Default = "Disable")

The Hardware P-State setting allows the user to select between OS and hardware-controlled P-states. Selecting Native Mode allows the OS to choose a P-state. Selecting Out of Band Mode allows the hardware to autonomously choose a P-state without OS guidance. Selecting Native Mode with No Legacy Support functions as Native Mode with no support for older hardware.

SNC (Sub NUMA Cluster): (Default = "Disable")

Auto supports 1-culster or 2-clusters depending on IMC interleave. SNC and IMC interleave both AUTO will suppor 1-cluster(XPT/KTI Prefecth enable) 2-IMC way interleave.SNC Enable supports full SNC (2 clusters and 1-way IMC interleave.

XPT Prefetch: (Default = "Disable")

This feature allows an LLC read request to be speculatively duplicated and sent concurrently to the appropriate MC (Memory Controller). These speculative MC reads are sent when an LLC miss is likely based on recent LLC history. IIf an LLC miss does occur, the MC read is already in flight so the requested data will be returned more quickly.

KTI Prefetch: (Default = "Enable")

KTI Prefetch enables memory read to start early on a DDR bus, where the KTI Rx path will directly create a Memory Speculative Read command to the memory controller.

Local/Remote Threshold: (Default = "Auto")

This feature allows the user to set the threshold for the Interrupt Request (IRQ) signal, which handles hardware interruptions.

Enforce POR: (Default = "POR")

Enable to enforce Plan Of Record restrictions for DDR4 frequency and voltage programming. Memory speeds will be capped at Intel guidelines. Disabling allows user selection of additional supported memory speeds.

Memory Frequency: (Default = "Auto")

Selects desired memory frequecy (within populated memory limits).

Interleave NVDIMMs: (Default = "Disabled")

Controls if NVDIMMs are interleaved together or not.

SDDC Plus One: (Default = "Disable")

Which is the enhanced feature to SDDC. Single Device Data Correction (SDDC) checks and corrects single-bit or multiple-bit (4-bit max.) memory faults that affect an entire single x4 DRAM device. SDDC Plus One will spare the faulty DRAM device out after an SDDC event has occurred. After the event, the SDDC+1 ECC mode is activated to protect against any additional memory failure caused by a 'single-bit' error in the same memory rank.

Patrol Scrub: (Default = "Enable")

Enable or disable the ability to proactively search the system memory, repairing correctable errors.