SPEC(R) CPU2017 Integer Rate Result Cisco Systems Cisco UCS B480 M5 (Intel Xeon Gold 6144, 3.50 GHz) CPU2017 License: 9019 Test date: Dec-2017 Test sponsor: Cisco Systems Hardware availability: Aug-2017 Tested by: Cisco Systems Software availability: Sep-2017 Base Base Base Peak Peak Peak Benchmarks Copies Run Time Rate Copies Run Time Rate --------------- ------- --------- --------- ------- --------- --------- 500.perlbench_r 64 597 171 * 64 481 212 * 500.perlbench_r 64 611 167 S 64 481 212 S 500.perlbench_r 64 595 171 S 64 482 211 S 502.gcc_r 64 450 201 S 64 374 242 * 502.gcc_r 64 451 201 S 64 375 241 S 502.gcc_r 64 450 201 * 64 374 242 S 505.mcf_r 64 368 281 S 64 361 286 S 505.mcf_r 64 361 287 S 64 370 279 * 505.mcf_r 64 364 284 * 64 377 274 S 520.omnetpp_r 64 633 133 S 64 629 134 S 520.omnetpp_r 64 633 133 * 64 630 133 * 520.omnetpp_r 64 633 133 S 64 660 127 S 523.xalancbmk_r 64 267 253 S 64 229 295 S 523.xalancbmk_r 64 270 251 * 64 229 295 * 523.xalancbmk_r 64 270 251 S 64 228 297 S 525.x264_r 64 247 453 * 64 238 470 S 525.x264_r 64 247 453 S 64 238 470 * 525.x264_r 64 248 451 S 64 237 474 S 531.deepsjeng_r 64 370 198 S 64 369 199 S 531.deepsjeng_r 64 371 198 * 64 375 196 S 531.deepsjeng_r 64 372 197 S 64 371 198 * 541.leela_r 64 551 192 S 64 547 194 * 541.leela_r 64 562 189 S 64 549 193 S 541.leela_r 64 552 192 * 64 543 195 S 548.exchange2_r 64 380 442 S 64 378 444 S 548.exchange2_r 64 380 442 * 64 379 443 * 548.exchange2_r 64 379 443 S 64 379 442 S 557.xz_r 64 427 162 * 64 425 163 S 557.xz_r 64 427 162 S 64 459 151 * 557.xz_r 64 425 163 S 64 459 150 S ================================================================================= 500.perlbench_r 64 597 171 * 64 481 212 * 502.gcc_r 64 450 201 * 64 374 242 * 505.mcf_r 64 364 284 * 64 370 279 * 520.omnetpp_r 64 633 133 * 64 630 133 * 523.xalancbmk_r 64 270 251 * 64 229 295 * 525.x264_r 64 247 453 * 64 238 470 * 531.deepsjeng_r 64 371 198 * 64 371 198 * 541.leela_r 64 552 192 * 64 547 194 * 548.exchange2_r 64 380 442 * 64 379 443 * 557.xz_r 64 427 162 * 64 459 151 * SPECrate2017_int_base 229 SPECrate2017_int_peak 242 HARDWARE -------- CPU Name: Intel Xeon Gold 6144 Max MHz.: 4200 Nominal: 3500 Enabled: 32 cores, 4 chips, 2 threads/core Orderable: 2,4 Chips Cache L1: 32 KB I + 32 KB D on chip per core L2: 1 MB I+D on chip per core L3: 24.75 MB I+D on chip per chip Other: None Memory: 768 GB (48 x 16 GB 2Rx4 PC4-2666V-R) Storage: 1 x 600 GB SAS HDD, 10K RPM Other: None SOFTWARE -------- OS: SUSE Linux Enterprise Server 12 SP2 (x86_64) 4.4.21-69-default Compiler: C/C++: Version 18.0.0.128 of Intel C/C++ Compiler for Linux; Fortran: Version 18.0.0.128 of Intel Fortran Compiler for Linux Parallel: No Firmware: Version 3.2.2a released Sep-2017 File System: xfs System State: Run level 3 (multi-user) Base Pointers: 64-bit Peak Pointers: 32/64-bit Other: jemalloc: jemalloc memory allocator library V5.0.1; jemalloc: configured and built at default for 32bit (i686) and 64bit (x86_64) targets; jemalloc: built with the RedHat Enterprise 7.4, and the system compiler gcc 4.8.5; jemalloc: sources avilable from jemalloc.net or https://github.com/jemalloc/jemalloc/releases Submit Notes ------------ The numactl mechanism was used to bind copies to processors. The config file option 'submit' was used to generate numactl commands to bind each copy to a specific processor. For details, please see the config file. Operating System Notes ---------------------- Stack size set to unlimited using "ulimit -s unlimited" General Notes ------------- Environment variables set by runcpu before the start of the run: LD_LIBRARY_PATH = "/opt/cpu2017/lib/ia32:/opt/cpu2017/lib/intel64:/opt/cpu2017/je5.0.1-32:/opt/cpu2017/je5.0.1-64" Binaries compiled on a system with 1x Intel Core i7-4790 CPU + 32GB RAM memory using Redhat Enterprise Linux 7.4 Transparent Huge Pages enabled by default Prior to runcpu invocation Filesystem page cache synced and cleared with: sync; echo 3> /proc/sys/vm/drop_caches runcpu command invoked through numactl i.e.: numactl --interleave=all runcpu No: The test sponsor attests, as of date of publication, that CVE-2017-5754 (Meltdown) is mitigated in the system as tested and documented. No: The test sponsor attests, as of date of publication, that CVE-2017-5753 (Spectre variant 1) is mitigated in the system as tested and documented. No: The test sponsor attests, as of date of publication, that CVE-2017-5715 (Spectre variant 2) is mitigated in the system as tested and documented. This benchmark result is intended to provide perspective on past performance using the historical hardware and/or software described on this result page. The system as described on this result page was formerly generally available. At the time of this publication, it may not be shipping, and/or may not be supported, and/or may fail to meet other tests of General Availability described in the SPEC OSG Policy document, http://www.spec.org/osg/policy.html This measured result may not be representative of the result that would be measured were this benchmark run with hardware and software available as of the publication date. Platform Notes -------------- BIOS Settings: Intel HyperThreading Technology set to Enabled CPU performance set to Enterprise Power Performance Tuning set to OS Controls SNC set to Enabled IMC Interleaving set to 1-way Interleave Patrol Scrub set to Disabled Sysinfo program /opt/cpu2017/bin/sysinfo Rev: r5797 of 2017-06-14 96c45e4568ad54c135fd618bcc091c0f running on linux-qiwr Wed Dec 20 20:14:06 2017 SUT (System Under Test) info as seen by some common utilities. For more information on this section, see https://www.spec.org/cpu2017/Docs/config.html#sysinfo From /proc/cpuinfo model name : Intel(R) Xeon(R) Gold 6144 CPU @ 3.50GHz 4 "physical id"s (chips) 64 "processors" cores, siblings (Caution: counting these is hw and system dependent. The following excerpts from /proc/cpuinfo might not be reliable. Use with caution.) cpu cores : 8 siblings : 16 physical 0: cores 0 2 3 9 16 19 26 27 physical 1: cores 0 2 3 9 16 19 26 27 physical 2: cores 0 2 3 9 16 19 26 27 physical 3: cores 0 2 3 9 16 19 26 27 From lscpu: Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 64 On-line CPU(s) list: 0-63 Thread(s) per core: 2 Core(s) per socket: 8 Socket(s): 4 NUMA node(s): 8 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Gold 6144 CPU @ 3.50GHz Stepping: 4 CPU MHz: 3889.850 CPU max MHz: 4200.0000 CPU min MHz: 1200.0000 BogoMIPS: 7000.01 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 25344K NUMA node0 CPU(s): 0,1,3,4,32,33,35,36 NUMA node1 CPU(s): 2,5-7,34,37-39 NUMA node2 CPU(s): 8,9,11,12,40,41,43,44 NUMA node3 CPU(s): 10,13-15,42,45-47 NUMA node4 CPU(s): 16,17,19,20,48,49,51,52 NUMA node5 CPU(s): 18,21-23,50,53-55 NUMA node6 CPU(s): 24,25,27,28,56,57,59,60 NUMA node7 CPU(s): 26,29-31,58,61-63 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch ida arat epb pln pts dtherm hwp hwp_act_window hwp_epp hwp_pkg_req intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx avx512f avx512dq rdseed adx smap clflushopt clwb avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 cqm_llc cqm_occup_llc /proc/cpuinfo cache data cache size : 25344 KB From numactl --hardware WARNING: a numactl 'node' might or might not correspond to a physical chip. available: 8 nodes (0-7) node 0 cpus: 0 1 3 4 32 33 35 36 node 0 size: 95167 MB node 0 free: 94711 MB node 1 cpus: 2 5 6 7 34 37 38 39 node 1 size: 96760 MB node 1 free: 96353 MB node 2 cpus: 8 9 11 12 40 41 43 44 node 2 size: 96760 MB node 2 free: 96354 MB node 3 cpus: 10 13 14 15 42 45 46 47 node 3 size: 96760 MB node 3 free: 96356 MB node 4 cpus: 16 17 19 20 48 49 51 52 node 4 size: 96760 MB node 4 free: 96357 MB node 5 cpus: 18 21 22 23 50 53 54 55 node 5 size: 96760 MB node 5 free: 96370 MB node 6 cpus: 24 25 27 28 56 57 59 60 node 6 size: 96760 MB node 6 free: 96371 MB node 7 cpus: 26 29 30 31 58 61 62 63 node 7 size: 96757 MB node 7 free: 96358 MB node distances: node 0 1 2 3 4 5 6 7 0: 10 11 31 31 21 21 21 21 1: 11 10 31 31 21 21 21 21 2: 31 31 10 11 21 21 21 21 3: 31 31 11 10 21 21 21 21 4: 21 21 21 21 10 11 31 31 5: 21 21 21 21 11 10 31 31 6: 21 21 21 21 31 31 10 11 7: 21 21 21 21 31 31 11 10 From /proc/meminfo MemTotal: 791027744 kB HugePages_Total: 0 Hugepagesize: 2048 kB From /etc/*release* /etc/*version* SuSE-release: SUSE Linux Enterprise Server 12 (x86_64) VERSION = 12 PATCHLEVEL = 2 # This file is deprecated and will be removed in a future service pack or release. # Please check /etc/os-release for details about this release. os-release: NAME="SLES" VERSION="12-SP2" VERSION_ID="12.2" PRETTY_NAME="SUSE Linux Enterprise Server 12 SP2" ID="sles" ANSI_COLOR="0;32" CPE_NAME="cpe:/o:suse:sles:12:sp2" uname -a: Linux linux-qiwr 4.4.21-69-default #1 SMP Tue Oct 25 10:58:20 UTC 2016 (9464f67) x86_64 x86_64 x86_64 GNU/Linux run-level 3 Dec 20 08:30 SPEC is set to: /opt/cpu2017 Filesystem Type Size Used Avail Use% Mounted on /dev/sda1 xfs 280G 29G 251G 11% / Additional information from dmidecode follows. WARNING: Use caution when you interpret this section. The 'dmidecode' program reads system data which is "intended to allow hardware to be accurately determined", but the intent may not be met, as there are frequent changes to hardware, firmware, and the "DMTF SMBIOS" standard. BIOS Cisco Systems, Inc. B480M5.3.2.2a.0.0919171641 09/19/2017 Memory: 48x 0xCE00 M393A2G40EB2-CTD 16 GB 2 rank 2666 (End of data from sysinfo program) Compiler Version Notes ---------------------- ============================================================================== CC 500.perlbench_r(base) 502.gcc_r(base) 505.mcf_r(base, peak) 525.x264_r(base, peak) 557.xz_r(base, peak) ------------------------------------------------------------------------------ icc (ICC) 18.0.0 20170811 Copyright (C) 1985-2017 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== CC 500.perlbench_r(peak) 502.gcc_r(peak) ------------------------------------------------------------------------------ icc (ICC) 18.0.0 20170811 Copyright (C) 1985-2017 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== CXXC 520.omnetpp_r(base) 523.xalancbmk_r(base) 531.deepsjeng_r(base) 541.leela_r(base) ------------------------------------------------------------------------------ icpc (ICC) 18.0.0 20170811 Copyright (C) 1985-2017 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== CXXC 520.omnetpp_r(peak) 523.xalancbmk_r(peak) 531.deepsjeng_r(peak) 541.leela_r(peak) ------------------------------------------------------------------------------ icpc (ICC) 18.0.0 20170811 Copyright (C) 1985-2017 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ ============================================================================== FC 548.exchange2_r(base, peak) ------------------------------------------------------------------------------ ifort (IFORT) 18.0.0 20170811 Copyright (C) 1985-2017 Intel Corporation. All rights reserved. ------------------------------------------------------------------------------ Base Compiler Invocation ------------------------ C benchmarks: icc C++ benchmarks: icpc Fortran benchmarks: ifort Base Portability Flags ---------------------- 500.perlbench_r: -DSPEC_LP64 -DSPEC_LINUX_X64 502.gcc_r: -DSPEC_LP64 505.mcf_r: -DSPEC_LP64 520.omnetpp_r: -DSPEC_LP64 523.xalancbmk_r: -DSPEC_LP64 -DSPEC_LINUX 525.x264_r: -DSPEC_LP64 531.deepsjeng_r: -DSPEC_LP64 541.leela_r: -DSPEC_LP64 548.exchange2_r: -DSPEC_LP64 557.xz_r: -DSPEC_LP64 Base Optimization Flags ----------------------- C benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/usr/local/je5.0.1-64/lib -ljemalloc C++ benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/usr/local/je5.0.1-64/lib -ljemalloc Fortran benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -nostandard-realloc-lhs -align array32byte -L/usr/local/je5.0.1-64/lib -ljemalloc Base Other Flags ---------------- C benchmarks: -m64 -std=c11 C++ benchmarks: -m64 Fortran benchmarks: -m64 Peak Compiler Invocation ------------------------ C benchmarks: icc C++ benchmarks: icpc Fortran benchmarks: ifort Peak Portability Flags ---------------------- 500.perlbench_r: -DSPEC_LP64 -DSPEC_LINUX_X64 502.gcc_r: -D_FILE_OFFSET_BITS=64 505.mcf_r: -DSPEC_LP64 520.omnetpp_r: -DSPEC_LP64 523.xalancbmk_r: -D_FILE_OFFSET_BITS=64 -DSPEC_LINUX 525.x264_r: -DSPEC_LP64 531.deepsjeng_r: -DSPEC_LP64 541.leela_r: -DSPEC_LP64 548.exchange2_r: -DSPEC_LP64 557.xz_r: -DSPEC_LP64 Peak Optimization Flags ----------------------- C benchmarks: 500.perlbench_r: -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-mem-layout-trans=3 -fno-strict-overflow -L/usr/local/je5.0.1-64/lib -ljemalloc 502.gcc_r: -L/opt/intel/compilers_and_libraries_2018/linux/lib/ia32 -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/usr/local/je5.0.1-32/lib -ljemalloc 505.mcf_r: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/usr/local/je5.0.1-64/lib -ljemalloc 525.x264_r: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -fno-alias -L/usr/local/je5.0.1-64/lib -ljemalloc 557.xz_r: Same as 505.mcf_r C++ benchmarks: 520.omnetpp_r: -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/usr/local/je5.0.1-64/lib -ljemalloc 523.xalancbmk_r: -L/opt/intel/compilers_and_libraries_2018/linux/lib/ia32 -Wl,-z,muldefs -prof-gen(pass 1) -prof-use(pass 2) -ipo -xCORE-AVX512 -O3 -no-prec-div -qopt-mem-layout-trans=3 -L/usr/local/je5.0.1-32/lib -ljemalloc 531.deepsjeng_r: Same as 520.omnetpp_r 541.leela_r: Same as 520.omnetpp_r Fortran benchmarks: -Wl,-z,muldefs -xCORE-AVX512 -ipo -O3 -no-prec-div -qopt-mem-layout-trans=3 -nostandard-realloc-lhs -align array32byte -L/usr/local/je5.0.1-64/lib -ljemalloc Peak Other Flags ---------------- C benchmarks (except as noted below): -m64 -std=c11 502.gcc_r: -m32 -std=c11 C++ benchmarks (except as noted below): -m64 523.xalancbmk_r: -m32 Fortran benchmarks: -m64 The flags files that were used to format this result can be browsed at http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.html http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.html You can also download the XML flags sources by saving the following links: http://www.spec.org/cpu2017/flags/Intel-ic18.0-official-linux64.xml http://www.spec.org/cpu2017/flags/Cisco-Platform-Settings-V1.2-revH.xml SPEC is a registered trademark of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ---------------------------------------------------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact info@spec.org. Copyright 2017-2018 Standard Performance Evaluation Corporation Tested with SPEC CPU2017 v1.0.2 on 2017-12-20 20:14:05-0500. Report generated on 2018-10-31 16:58:07 by CPU2017 ASCII formatter v6067. Originally published on 2018-02-23.