![[user]](https://www.spec.org/auto/hpc2021/images/user.png)
The Intel MPI C driver configured for use with the Intel oneAPI C compiler.
The Intel MPI C++ driver configured for use with the Intel oneAPI C++ compiler.
The Intel MPI Fortran driver configured for use with the Intel oneAPI Fortran compiler.
The Intel MPI C driver configured for use with the Intel oneAPI C compiler.
The Intel MPI C++ driver configured for use with the Intel oneAPI C++ compiler.
The Intel MPI Fortran driver configured for use with the Intel oneAPI Fortran compiler.
![[suite]](https://www.spec.org/auto/hpc2021/images/suite.png)
Use the MPI version of the code.
Use the MPI version of the code.
![[benchmark]](https://www.spec.org/auto/hpc2021/images/benchmark.png)
Disable use of reduction with variable array reduction variable (OpenMP 4.5, OpenACC 2.7) even if compiler reports support.
Use the MPI version of the code.
Use the MPI version of the code.
Use the MPI version of the code.
Use the MPI version of the code.
Use the MPI version of the code.
Use the MPI version of the code.
Disable use of reduction with variable array reduction variable (OpenMP 4.5, OpenACC 2.7) even if compiler reports support.
Use the MPI version of the code.
Use the MPI version of the code.
Use the MPI version of the code.
Use the MPI version of the code.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Enable LTO (Link Time Optimization) in 'full' mode.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Definition of this macro indicates that the user selected to use the collapsed version of the directives. Valid only for LBM and Cloverleaf.
Definition of this macro indicates that the MPI implementation supports accelerator device-to-device transfers. Used in conjuction when using OpenACC or OpenMP w/ target offload.
When using the collapse clause on a loop nest the default behavior is to automatically extend the representation of the loop counter to 64 bits for the cases where the sizes of the collapsed loops are not known at compile time. To prevent this conservative choice and use at most 32 bits, compile your program with the -fopenmp-optimistic-collapse.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Enable LTO (Link Time Optimization) in 'full' mode.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Definition of this macro indicates that the user selected to use the collapsed version of the directives. Valid only for LBM and Cloverleaf.
Definition of this macro indicates that the MPI implementation supports accelerator device-to-device transfers. Used in conjuction when using OpenACC or OpenMP w/ target offload.
Definition of this macro indicates that the user selected to use the collapsed version of the directives. Valid only for LBM and Cloverleaf.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Definition of this macro indicates that the MPI implementation supports accelerator device-to-device transfers. Used in conjuction when using OpenACC or OpenMP w/ target offload.
Enable LTO (Link Time Optimization) in 'full' mode.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Enables the loop optimizer and auto-vectorization for OpenMP offloading device compilation when option O2 or higher is set or specified.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Enable LTO (Link Time Optimization) in 'full' mode.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Definition of this macro indicates that the user selected to use the collapsed version of the directives. Valid only for LBM and Cloverleaf.
Definition of this macro indicates that the MPI implementation supports accelerator device-to-device transfers. Used in conjuction when using OpenACC or OpenMP w/ target offload.
When using the collapse clause on a loop nest the default behavior is to automatically extend the representation of the loop counter to 64 bits for the cases where the sizes of the collapsed loops are not known at compile time. To prevent this conservative choice and use at most 32 bits, compile your program with the -fopenmp-optimistic-collapse.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Enable LTO (Link Time Optimization) in 'full' mode.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Definition of this macro indicates that the user selected to use the collapsed version of the directives. Valid only for LBM and Cloverleaf.
Definition of this macro indicates that the MPI implementation supports accelerator device-to-device transfers. Used in conjuction when using OpenACC or OpenMP w/ target offload.
When using the collapse clause on a loop nest the default behavior is to automatically extend the representation of the loop counter to 64 bits for the cases where the sizes of the collapsed loops are not known at compile time. To prevent this conservative choice and use at most 32 bits, compile your program with the -fopenmp-optimistic-collapse.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Enable LTO (Link Time Optimization) in 'full' mode.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Definition of this macro indicates that the user selected to use the collapsed version of the directives. Valid only for LBM and Cloverleaf.
Definition of this macro indicates that the MPI implementation supports accelerator device-to-device transfers. Used in conjuction when using OpenACC or OpenMP w/ target offload.
Definition of this macro indicates that the user selected to use the collapsed version of the directives. Valid only for LBM and Cloverleaf.
Optimize for maximum speed and enable more aggressive optimizations that may not improve performance on some programs.
Code is optimized for Intel(R) processors with support for AVX instructions. May generate Intel® AVX-12 Foundation instructions,Intel® AVX-512 Conflict Detectio instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-51 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2,VX SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
Definition of this macro indicates that the MPI implementation supports accelerator device-to-device transfers. Used in conjuction when using OpenACC or OpenMP w/ target offload.
Enable LTO (Link Time Optimization) in 'full' mode.
Specifies preferred 512b vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.
Allow aggressive, lossy floating-point optimizations.
Enable the compiler to generate multi-threaded code based on the OpenMP* directives. Similar behavior was granted by -qopenmp in previous versions.
Enables offloading to a specified GPU target if OpenMP features have been enabled.
Is a target triple device name. The following triplets are supported.
spir64 - Tells the compiler to enable offloading to SPIR64-based devices.
spir64_x86_64 - Tells the compiler to enable offloading to Intel CPUs.
spir64_gen - Tells the compiler to enable offloading to Intel Proessor Graphics.
-ftarget-register-alloc-mode=device-name:reg-mode[, device-name:reg-mode][,...]
device-name - Is the device name. Currently, you can only specify the following: pvc Indicates a Ponte Vecchio (PVC) device.
reg-mode - Is the register allocation mode. It can be any of the following:
default - Tells the target backend to not impose any specification when choosing a register allocation mode.
small - Tells the target backend to select small register allocation mode (for PVC, this means to use the 128 register file).
large - Tells the target backend to select large register allocation mode (for PVC, this means to use the 256 register file).
auto - Tells the target backend to use internal heuristics to select a register allocation mode based on kernel analysis.
Pass arg to the OpenMP based target backend.
-device <arch> - set target device.
-revision_id <revision_id> - Target stepping. Can be decimal or hexadecimal value.
-cl-fast-relaxed-math - Sets the optimization options -cl-finite-math-only and -cl-unsafe-math-optimizations, which enable optimizations for floating-point arithmetic that may violate the IEEE 754 standard and the OpenCL numerical compliance requirements.
The device and revision_id options are only needed for AOT mode.
Enables the loop optimizer and auto-vectorization for OpenMP offloading device compilation when option O2 or higher is set or specified.
Enable the specified warning.
Enable the specified warning.
Flag description origin markings:
|
Indicates that the flag description came from the user flags file. |
|
Indicates that the flag description came from the suite-wide flags file. |
|
Indicates that the flag description came from a per-benchmark flags file. |
For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2021-2025 Standard Performance Evaluation Corporation
Tested with SPEC hpc2021 v1.1.9.
Report generated on 2025-05-27 16:43:12 by SPEC hpc2021 flags formatter v112 .