SPEC(R) MPIM2007 Summary SGI SGI ICE X (Intel Xeon E5-2690 v3, 2.6 GHz) Thu Jul 24 18:04:46 2014 MPI2007 License: 14 Test date: Jul-2014 Test sponsor: SGI Hardware availability: Sep-2014 Tested by: SGI Software availability: Apr-2014 Base Base Base Peak Peak Peak Benchmarks Ranks Run Time Ratio Ranks Run Time Ratio -------------- ------ --------- --------- ------ --------- --------- 104.milc 96 78.1 20.0 S 104.milc 96 78.0 20.1 * 104.milc 96 78.0 20.1 S 107.leslie3d 96 202 25.9 S 107.leslie3d 96 198 26.4 S 107.leslie3d 96 199 26.3 * 113.GemsFDTD 96 177 35.7 S 113.GemsFDTD 96 175 36.1 * 113.GemsFDTD 96 174 36.2 S 115.fds4 96 92.5 21.1 * 115.fds4 96 92.6 21.1 S 115.fds4 96 92.3 21.1 S 121.pop2 96 156 26.5 * 121.pop2 96 156 26.5 S 121.pop2 96 157 26.4 S 122.tachyon 96 127 22.0 S 122.tachyon 96 128 21.9 S 122.tachyon 96 127 22.0 * 126.lammps 96 148 19.7 S 126.lammps 96 148 19.7 S 126.lammps 96 148 19.7 * 127.wrf2 96 168 46.4 S 127.wrf2 96 168 46.4 * 127.wrf2 96 169 46.1 S 128.GAPgeofem 96 65.5 31.5 * 128.GAPgeofem 96 66.0 31.3 S 128.GAPgeofem 96 65.4 31.6 S 129.tera_tf 96 133 20.9 S 129.tera_tf 96 133 20.8 S 129.tera_tf 96 133 20.9 * 130.socorro 96 68.7 55.5 S 130.socorro 96 66.9 57.0 * 130.socorro 96 66.9 57.0 S 132.zeusmp2 96 116 26.9 * 132.zeusmp2 96 116 26.8 S 132.zeusmp2 96 115 26.9 S 137.lu 96 108 34.1 S 137.lu 96 108 34.1 S 137.lu 96 108 34.1 * ============================================================================== 104.milc 96 78.0 20.1 * 107.leslie3d 96 199 26.3 * 113.GemsFDTD 96 175 36.1 * 115.fds4 96 92.5 21.1 * 121.pop2 96 156 26.5 * 122.tachyon 96 127 22.0 * 126.lammps 96 148 19.7 * 127.wrf2 96 168 46.4 * 128.GAPgeofem 96 65.5 31.5 * 129.tera_tf 96 133 20.9 * 130.socorro 96 66.9 57.0 * 132.zeusmp2 96 116 26.9 * 137.lu 96 108 34.1 * SPECmpiM_base2007 28.3 SPECmpiM_peak2007 Not Run BENCHMARK DETAILS ----------------- Type of System: Homogeneous Total Compute Nodes: 4 Total Chips: 8 Total Cores: 96 Total Threads: 96 Total Memory: 512 GB Base Ranks Run: 96 Minimum Peak Ranks: -- Maximum Peak Ranks: -- C Compiler: Intel C++ Composer XE 2013 for Linux, Version 14.0.3.174 Build 20140422 C++ Compiler: Intel C++ Composer XE 2013 for Linux Version 14.0.3.174 Build 20140422 Fortran Compiler: Intel Fortran Composer XE 2013 for Linux, Version 14.0.3.174 Build 20140422 Base Pointers: 64-bit Peak Pointers: Not Applicable MPI Library: SGI MPT 2.09 Patch 11049 Other MPI Info: OFED 1.5.4 Pre-processors: None Other Software: None Node Description: SGI ICE X IP-131 Compute Node =============================================== HARDWARE -------- Number of nodes: 4 Uses of the node: compute Vendor: SGI Model: SGI ICE X (Intel Xeon E6-2690 v3, 2.6 GHz) CPU Name: Intel Xeon E5-2690 v3 CPU(s) orderable: 1-2 chips Chips enabled: 2 Cores enabled: 24 Cores per chip: 12 Threads per core: 1 CPU Characteristics: 12 Core, 2.60 GHz, 9.6 GT/s QPI Intel Turbo Boost Technology up to 3.50 GHz Hyper-Threading Technology disabled CPU MHz: 2600 Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 256 KB I+D on chip per core L3 Cache: 30 MB I+D on chip per chip Other Cache: None Memory: 128 GB (8 x 16 GB 2Rx4 PC4-17000R-15, ECC) Disk Subsystem: None Other Hardware: None Adapter: Mellanox MT27500 with ConnectX-3 ASIC (PCIe x8 Gen3 8 GT/s) Number of Adapters: 2 Slot Type: PCIe x8 Gen3 Data Rate: InfiniBand 4x FDR Ports Used: 2 Interconnect Type: InfiniBand SOFTWARE -------- Adapter: Mellanox MT27500 with ConnectX-3 ASIC (PCIe x8 Gen3 8 GT/s) Adapter Driver: OFED-1.5.4 Adapter Firmware: 2.30.3000 Operating System: SUSE Linux Enterprise Server 11 SP3 (x86_64), Kernel 3.0.93-0.8-default Local File System: NFSv3 Shared File System: NFSv3 IPoIB System State: Multi-user, run level 3 Other Software: SGI Tempo Service Node 2.8.1, Build 709rp49.sles11sp3-1402182002 Node Description: SGI Rackable C1103-TY12 ========================================= HARDWARE -------- Number of nodes: 1 Uses of the node: fileserver Vendor: SGI Model: SGI Rackable C1103-TY12 (Intel Xeon X5670, 2.93 GHz) CPU Name: Intel Xeon X5670 CPU(s) orderable: 1-2 chips Chips enabled: 2 Cores enabled: 12 Cores per chip: 6 Threads per core: 2 CPU Characteristics: Intel Turbo Boost Technology up to 3.33 GHz Hyper-Threading Technology enabled CPU MHz: 2933 Primary Cache: 32 KB I + 32 KB D on chip per core Secondary Cache: 256 KB I+D on chip per chip L3 Cache: 12 MB I+D on chip per chip Other Cache: None Memory: 96 GB (12 * 8 GB 2Rx4 PC3-10600R-9, ECC) Disk Subsystem: 12 TB RAID 6 12 x 1 TB SATA (Seagate Constellation, 7200RPM) Other Hardware: None Adapter: Mellanox MT27500 with ConnectX-3 ASIC (PCIe x8 Gen3 8 GT/s) Number of Adapters: 2 Slot Type: PCIe x8 Gen3 Data Rate: InfiniBand 4x FDR Ports Used: 2 Interconnect Type: InfiniBand SOFTWARE -------- Adapter: Mellanox MT27500 with ConnectX-3 ASIC (PCIe x8 Gen3 8 GT/s) Adapter Driver: OFED-1.5.2 Adapter Firmware: 2.30.3000 Operating System: SUSE Linux Enterprise Server 11 SP1 (x86_64), Kernel 2.6.32.46-0.3-default Local File System: xfs Shared File System: -- System State: Multi-user, run level 3 Other Software: SGI Foundation Software 2.5, Build 705r10.sles11-1110192111 Interconnect Description: InfiniBand (MPI and I/O) ================================================== HARDWARE -------- Vendor: Mellanox Technologies and SGI Model: None Switch Model: SGI FDR Integrated IB Switch Blade 2SW9x27 with Mellanox SwitchX device 51000 Number of Switches: 2 Number of Ports: 36 Data Rate: InfiniBand 4x FDR Firmware: 09.02.3000 Topology: Enhanced Hypercube Primary Use: MPI and I/O traffic Submit Notes ------------ The config file option 'submit' was used. General Notes ------------- Software environment: export MPI_REQUEST_MAX=65536 export MPI_TYPE_MAX=32768 export MPI_IB_RAILS=2 ulimit -s unlimited BIOS settings: AMI BIOS version DY2E6044 Hyper-Threading Technology disabled Intel Turbo Boost Technology enabled (default) Intel Turbo Boost Technology activated with modprobe acpi_cpufreq cpupower frequency-set -u 2601MHz -d 2601MHz -g performance Job Placement: Each MPI job was assigned to a topologically compact set of nodes, i.e. the minimal needed number of switches was used for each job: 2 switches for up to 192 ranks, 4 switches for up to 384 ranks, 8 switches for 768 ranks, and 16 switches for 1536 ranks. Additional notes regarding interconnect: The Infiniband network consists of two independent planes, with half the switches in the system allocated to each plane. I/O traffic is restricted to one plane, while MPI traffic can use both planes. Base Compiler Invocation ------------------------ C benchmarks: icc C++ benchmarks: 126.lammps: icpc Fortran benchmarks: ifort Benchmarks using both Fortran and C: icc ifort Base Portability Flags ---------------------- 121.pop2: -DSPEC_MPI_CASE_FLAG 127.wrf2: -DSPEC_MPI_CASE_FLAG -DSPEC_MPI_LINUX 130.socorro: -assume nostd_intent_in Base Optimization Flags ----------------------- C benchmarks: -O3 -xCORE-AVX2 -no-prec-div C++ benchmarks: 126.lammps: -O3 -xCORE-AVX2 -no-prec-div -ansi-alias Fortran benchmarks: -O3 -xCORE-AVX2 -no-prec-div Benchmarks using both Fortran and C: -O3 -xCORE-AVX2 -no-prec-div Base Other Flags ---------------- C benchmarks: -lmpi C++ benchmarks: 126.lammps: -lmpi Fortran benchmarks: -lmpi Benchmarks using both Fortran and C: -lmpi The flags file that was used to format this result can be browsed at http://www.spec.org/mpi2007/flags/SGI_x86_64_Intel14_flags.20140908.html You can also download the XML flags source by saving the following link: http://www.spec.org/mpi2007/flags/SGI_x86_64_Intel14_flags.20140908.xml SPEC and SPEC MPI are registered trademarks of the Standard Performance Evaluation Corporation. All other brand and product names appearing in this result are trademarks or registered trademarks of their respective holders. ----------------------------------------------------------------------------- For questions about this result, please contact the tester. For other inquiries, please contact webmaster@spec.org. Copyright 2006-2010 Standard Performance Evaluation Corporation Tested with SPEC MPI2007 v2.0.1. Report generated on Mon Sep 8 13:46:03 2014 by MPI2007 ASCII formatter v1463. Originally published on 8 September 2014.