CPU2017 Flag Description
Dell Inc. PowerEdge R7425 (AMD EPYC 7251, 2.10 GHz)

This result has been formatted using multiple flags files. The "default header section" from each of them appears next.


Default header section from gcc

GNU Compiler Collection Flags

Flag descriptions for GCC, the GNU Compiler Collection

Note: The GNU Compiler Collection provides a wide array of compiler options, described in detail and readily available at https://gcc.gnu.org/onlinedocs/gcc/Option-Index.html#Option-Index and https://gcc.gnu.org/onlinedocs/gfortran/. This SPEC CPU flags file contains excerpts from and brief summaries of portions of that documentation.

SPEC's modifications are:
Copyright (C) 2006-2017 Standard Performance Evaluation Corporation

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with the Invariant Sections being "Funding Free Software", the Front-Cover Texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is included in your SPEC CPU kit at $SPEC/Docs/licenses/FDL.v1.3 and on the web at http://www.spec.org/cpu2017/Docs/licenses/FDL.v1.3. A copy of "Funding Free Software" is on your SPEC CPU kit at $SPEC/Docs/licenses/FundingFreeSW and on the web at http://www.spec.org/cpu2017/Docs/licenses/FundingFreeSW.

(a) The FSF's Front-Cover Text is:

A GNU Manual

(b) The FSF's Back-Cover Text is:

You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development.


Default header section from aocc100-flags-revC-I

AMD Optimizing C/C++ Compiler Suite SPEC CPU2017 Flag Description

Compilers: AOCC Suite


Base Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Peak Compiler Invocation

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Base Portability Flags

503.bwaves_r

507.cactuBSSN_r

508.namd_r

510.parest_r

511.povray_r

519.lbm_r

521.wrf_r

526.blender_r

527.cam4_r

538.imagick_r

544.nab_r

549.fotonik3d_r

554.roms_r


Peak Portability Flags

503.bwaves_r

507.cactuBSSN_r

508.namd_r

510.parest_r

511.povray_r

519.lbm_r

521.wrf_r

526.blender_r

527.cam4_r

538.imagick_r

544.nab_r

549.fotonik3d_r

554.roms_r


Base Optimization Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Peak Optimization Flags

C benchmarks

C++ benchmarks

Fortran benchmarks

Benchmarks using both Fortran and C

521.wrf_r

527.cam4_r

Benchmarks using both C and C++

Benchmarks using Fortran, C, and C++


Implicitly Included Flags

This section contains descriptions of flags that were included implicitly by other flags, but which do not have a permanent home at SPEC.


Commands and Options Used to Submit Benchmark Runs

This result has been formatted using multiple flags files. The "submit command" from each of them appears next.


Submit command from gcc

GNU Compiler Collection Flags

SPECrate runs might use one of these methods to bind processes to specific processors, depending on the config file.


Submit command from aocc100-flags-revC-I

AMD Optimizing C/C++ Compiler Suite SPEC CPU2017 Flag Description

Using numactl to bind processes and memory to cores

For multi-copy runs or single copy runs on systems with multiple sockets, it is advantageous to bind a process to a particular core. Otherwise, the OS may arbitrarily move your process from one core to another. This can effect performance. To help, SPEC allows the use of a "submit" command where users can specify a utility to use to bind processes. We have found the utility 'numactl' to be the best choice.

numactl runs processes with a specific NUMA scheduling or memory placement policy. The policy is set for a command and inherited by all of its children. The numactl flag "--physcpubind" specifies which core(s) to bind the process. "-l" instructs numactl to keep a process memory on the local node while "-m" specifies which node(s) to place a process memory. For full details on using numactl, please refer to your Linux documentation, 'man numactl'

Note that some versions of numactl, particularly the version found on SLES 10, we have found that the utility incorrectly interprets application arguments as it's own. For example, with the command "numactl --physcpubind=0 -l a.out -m a", numactl will interpret a.out's "-m" option as it's own "-m" option. To work around this problem, a user can put the command to be run in a shell script and then run the shell script using numactl. For example: "echo 'a.out -m a' > run.sh ; numactl --physcpubind=0 bash run.sh"


Commands and Options Used for Feedback-Directed Optimization

No special commands are needed for feedback-directed optimization, other than the compiler profile  flags.


Shell, Environment, and Other Software Settings

This result has been formatted using multiple flags files. The "sw environment" from each of them appears next.


Sw environment from gcc

GNU Compiler Collection Flags

One or more of the following may have been used in the run. If so, it will be listed in the notes sections. Here is a brief guide to understanding them:


Sw environment from aocc100-flags-revC-I

AMD Optimizing C/C++ Compiler Suite SPEC CPU2017 Flag Description

Transparent Huge Pages (THP)

THP is an abstraction layer that automates most aspects of creating, managing, and using huge pages. THP is designed to hide much of the complexity in using huge pages from system administrators and developers, as normal huge pages must be assigned at boot time, can be difficult to manage manually, and often require significant changes to code in order to be used effectively. Most recent Linux OS releases have THP enabled by default

Linux Huge Page settings

If you need finer control and manually set the Huge Pages you can follow the below steps:

Note that further information about huge pages may be found in your Linux documentation file: /usr/src/linux/Documentation/vm/hugetlbpage.txt

ulimit -s <n>

Sets the stack size to n kbytes, or unlimited to allow the stack size to grow without limit.

ulimit -l <n>

Sets the maximum size of memory that may be locked into physical memory.

OMP_NUM_THREADS

Sets the maximum number of OpenMP parallel threads applications based on OpenMP may use.

powersave -f (on SuSE)

Makes the powersave daemon set the CPUs to the highest supported frequency.

/etc/init.d/cpuspeed stop (on Red Hat)

Disables the cpu frequency scaling program in order to set the CPUs to the highest supported frequency.

LD_LIBRARY_PATH

An environment variable set to include the LLVM, JEMalloc and SmartHeap libraries used during compilation of the binaries. This environment variable setting is not needed when building the binaries on the system under test.

kernel/randomize_va_space

This option can be used to select the type of process address space randomization that is used in the system, for architectures that support this feature.
*** 0 - Turn the process address space randomization off. This is the default for architectures that do not support this feature anyways, and kernels that are booted with the "norandmaps" parameter.
*** 1 - Make the addresses of mmap base, stack and VDSO page randomized. This, among other things, implies that shared libraries will be loaded to random addresses. Also for PIE-linked binaries, the location of code start is randomized. This is the default if the CONFIG_COMPAT_BRK option is enabled.
*** 2 - Additionally enable heap randomization. This is the default if CONFIG_COMPAT_BRK is disabled.

MALLOC_CONF

An environment variable set to tune the jemalloc allocation strategy during the execution of the binaries. This environment variable setting is not needed when building the binaries on the system under test.


Firmware / BIOS / Microcode Settings

Memory Interleaving:

DISABLED-When memory interleave is disable 4 NUMA nodes will be seen as in the case for channel interleaving but the memory will not be interleaved yet stacked next to one another. CHANNEL INTERLEAVING-Channel interleaving is also available with all configurations and is the intra-die memory interleave option and is the default setting for Dell EMC platforms. With channel interleaving the memory behind each UMC will be interleaved and seen as 1 NUMA domain per die. This will generated with 4 NUMA domains per socket. DIE INTERLEAVING-Die interleaving is available for on all configurations and is the intra-socket memory interleave option that create one NUMA domain for all the 4 dies on socket. In a 2 processor configuration this will produce 2 NUMA domains, one domain pertaining to each socket providing customers with the first option for NUMA configuration. In a one socket platform die interleaving will be the maximum option of memory interleaving, and will produce one memory domain also producing a non-NUMA configuration. SOCKET INTERLEAVING-Socket interleaving is memory interleave option meant only for inter-socket memory interleaving, and is only available with a 2 processor configurations. In this configuration memory across both sockets will be seen as a single memory domain producing a non-NUMA configuration

Virtualization technology:

When set to Enabled, the BIOS will enable processor Virtualization features and provide the virtualization support to the Operating System (OS) through the DMAR table. In general, only virtualized environments such as VMware(r) ESX (tm), Microsoft Hyper-V(r) , Red Hat(r) KVM, and other virtualized operating systems will take advantage of these features. Disabling this feature is not known to significantly alter the performance or power characteristics of the system, so leaving this option Enabled is advised for most cases.

System Profile:

When set to Custom, you can change setting of each option. Under Custom mode when C state is enabled, Monitor/Mwait should also be enabled.

CPU Power Management:

Maximum Performance is typically selected for performance-centric workloads where it is acceptable to consume additional power to achieve the highest possible performance for the computing environment. This mode drives processor frequency to the maximum across all cores (although idled cores can still be frequency reduced by C-state enforcement through BIOS or OS mechanisms if enabled). This mode also offers the lowest latency of the CPU Power Management Mode options, so is always preferred.

Memory Frequency:

Governs the BIOS memory frequency. The variables that govern maximum memory frequency include the maximum rated frequency of the DIMMs, the DIMMs per channel population, the processor choice, and this BIOS option. Additional power savings can be achieved by reducing the memory frequency, at the expense of reduced performance.

Turbo Boost:

Governs the Boost Technology. This feature allows teh processor cores to be automatically clocked up in frequency beyond the advertised processor speed. The amount of increased frequency (or 'turbo upside') one can expect from an EPYC processor depends on the fewer cores being exercised with work the higher the potential turbo upside. The potential drawback for Boost are mainly centered on increased power consumption and possible frequency jitter that can affect a small minority of latency-sensitive environments.

C States:

C States allow the processor to enter lower power states when idle. When set to Enabled (OS controlled) or when set to Autonomous (if Hardware controlled is supported), the processor can operate in all available Power States to save power, but my increase memory latency and frequency jitter.

Memory Patrol Scrub:

Patrol Scrubbing searches the memory for errors and repairs correctable errors to prevent the accumulation of memory errors. When set to Disabled, no patrol scrubbing will occur. When set to Standard Mode, the entire memory array will be scrubbed once in a 24 hour period. When set to Extended Mode, the entire memory array will be scrubbed more frequently to further increase system reliability.

Memory Refresh Rate:

The memory controller will periodically refresh the data in memory. The frequency at which memory is normally refreshed is referred to as 1X refresh rate. When memory modules are operating at a higher than normal temperature or to further increase system reliability, the refresh rate can be set to 2X, but may have a negative impact on memory subsystem performance under some circumstances.

PCI ASPM L1 Link Power Management:

When enabled, PCIe Advanced State Power Management (ASPM) can reduce overall system power a bit while slightly reducing system performance.

NOTE: Some devices may not perform properly (they may hang or cause the system to hang) when ASPM is enable, for this reason L1 will only be enabled for validated qualified cards.


Flag description origin markings:

[user] Indicates that the flag description came from the user flags file.
[suite] Indicates that the flag description came from the suite-wide flags file.
[benchmark] Indicates that the flag description came from a per-benchmark flags file.

The flags files that were used to format this result can be browsed at
http://www.spec.org/cpu2017/flags/gcc.2018-02-16.html,
http://www.spec.org/cpu2017/flags/aocc100-flags-revC-I.2018-02-16.html,
http://www.spec.org/cpu2017/flags/amd1704-Dell-platform-revB-I.html.

You can also download the XML flags sources by saving the following links:
http://www.spec.org/cpu2017/flags/gcc.2018-02-16.xml,
http://www.spec.org/cpu2017/flags/aocc100-flags-revC-I.2018-02-16.xml,
http://www.spec.org/cpu2017/flags/amd1704-Dell-platform-revB-I.xml.


For questions about the meanings of these flags, please contact the tester.
For other inquiries, please contact info@spec.org
Copyright 2017-2018 Standard Performance Evaluation Corporation
Tested with SPEC CPU2017 v1.0.2.
Report generated on 2018-10-31 17:41:51 by SPEC CPU2017 flags formatter v5178.